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* Patches by Xianghua Xiao, 15 Oct 2003:
[people/ms/u-boot.git] / board / icecube / flash.c
1 /*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25
26 flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
27
28 /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
29 * has nothing to do with the flash chip being 8-bit or 16-bit.
30 */
31 #ifdef CONFIG_FLASH_16BIT
32 typedef unsigned short FLASH_PORT_WIDTH;
33 typedef volatile unsigned short FLASH_PORT_WIDTHV;
34 #define FLASH_ID_MASK 0xFFFF
35 #else
36 typedef unsigned char FLASH_PORT_WIDTH;
37 typedef volatile unsigned char FLASH_PORT_WIDTHV;
38 #define FLASH_ID_MASK 0xFF
39 #endif
40
41 #define FPW FLASH_PORT_WIDTH
42 #define FPWV FLASH_PORT_WIDTHV
43
44 #define ORMASK(size) ((-size) & OR_AM_MSK)
45
46 #define FLASH_CYCLE1 0x0555
47 #define FLASH_CYCLE2 0x02aa
48
49 /*-----------------------------------------------------------------------
50 * Functions
51 */
52 static ulong flash_get_size(FPWV *addr, flash_info_t *info);
53 static void flash_reset(flash_info_t *info);
54 static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
55 static flash_info_t *flash_get_info(ulong base);
56
57 /*-----------------------------------------------------------------------
58 * flash_init()
59 *
60 * sets up flash_info and returns size of FLASH (bytes)
61 */
62 unsigned long flash_init (void)
63 {
64 unsigned long size = 0;
65 int i;
66 extern void flash_preinit(void);
67 extern void flash_afterinit(ulong);
68 ulong flashbase = CFG_FLASH_BASE;
69
70 flash_preinit();
71
72 /* Init: no FLASHes known */
73 for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
74 memset(&flash_info[i], 0, sizeof(flash_info_t));
75
76 flash_info[i].size =
77 flash_get_size((FPW *)flashbase, &flash_info[i]);
78
79 size += flash_info[i].size;
80 flashbase += 0x800000;
81 }
82 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
83 /* monitor protection ON by default */
84 flash_protect(FLAG_PROTECT_SET,
85 CFG_MONITOR_BASE,
86 CFG_MONITOR_BASE+monitor_flash_len-1,
87 flash_get_info(CFG_MONITOR_BASE));
88 #endif
89
90 #ifdef CFG_ENV_IS_IN_FLASH
91 /* ENV protection ON by default */
92 flash_protect(FLAG_PROTECT_SET,
93 CFG_ENV_ADDR,
94 CFG_ENV_ADDR+CFG_ENV_SIZE-1,
95 flash_get_info(CFG_ENV_ADDR));
96 #endif
97
98
99 flash_afterinit(size);
100 return size ? size : 1;
101 }
102
103 /*-----------------------------------------------------------------------
104 */
105 static void flash_reset(flash_info_t *info)
106 {
107 FPWV *base = (FPWV *)(info->start[0]);
108
109 /* Put FLASH back in read mode */
110 if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
111 *base = (FPW)0x00FF00FF; /* Intel Read Mode */
112 else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
113 *base = (FPW)0x00F000F0; /* AMD Read Mode */
114 }
115
116 /*-----------------------------------------------------------------------
117 */
118
119 static flash_info_t *flash_get_info(ulong base)
120 {
121 int i;
122 flash_info_t * info;
123
124 for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
125 info = & flash_info[i];
126 if (info->size &&
127 info->start[0] <= base && base <= info->start[0] + info->size - 1)
128 break;
129 }
130
131 return i == CFG_MAX_FLASH_BANKS ? 0 : info;
132 }
133
134 /*-----------------------------------------------------------------------
135 */
136
137 void flash_print_info (flash_info_t *info)
138 {
139 int i;
140 uchar *boottype;
141 uchar *bootletter;
142 uchar *fmt;
143 uchar botbootletter[] = "B";
144 uchar topbootletter[] = "T";
145 uchar botboottype[] = "bottom boot sector";
146 uchar topboottype[] = "top boot sector";
147
148 if (info->flash_id == FLASH_UNKNOWN) {
149 printf ("missing or unknown FLASH type\n");
150 return;
151 }
152
153 switch (info->flash_id & FLASH_VENDMASK) {
154 case FLASH_MAN_AMD: printf ("AMD "); break;
155 case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
156 case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
157 case FLASH_MAN_SST: printf ("SST "); break;
158 case FLASH_MAN_STM: printf ("STM "); break;
159 case FLASH_MAN_INTEL: printf ("INTEL "); break;
160 default: printf ("Unknown Vendor "); break;
161 }
162
163 /* check for top or bottom boot, if it applies */
164 if (info->flash_id & FLASH_BTYPE) {
165 boottype = botboottype;
166 bootletter = botbootletter;
167 }
168 else {
169 boottype = topboottype;
170 bootletter = topbootletter;
171 }
172
173 switch (info->flash_id & FLASH_TYPEMASK) {
174 case FLASH_AMDLV065D:
175 fmt = "29LV065 (64 Mbit, uniform sectors)\n";
176 break;
177 default:
178 fmt = "Unknown Chip Type\n";
179 break;
180 }
181
182 printf (fmt, bootletter, boottype);
183
184 printf (" Size: %ld MB in %d Sectors\n",
185 info->size >> 20,
186 info->sector_count);
187
188 printf (" Sector Start Addresses:");
189
190 for (i=0; i<info->sector_count; ++i) {
191 if ((i % 5) == 0) {
192 printf ("\n ");
193 }
194
195 printf (" %08lX%s", info->start[i],
196 info->protect[i] ? " (RO)" : " ");
197 }
198
199 printf ("\n");
200 }
201
202 /*-----------------------------------------------------------------------
203 */
204
205 /*
206 * The following code cannot be run from FLASH!
207 */
208
209 ulong flash_get_size (FPWV *addr, flash_info_t *info)
210 {
211 int i;
212 FPWV* addr2;
213
214 /* Write auto select command: read Manufacturer ID */
215 /* Write auto select command sequence and test FLASH answer */
216 addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
217 addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
218 addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
219
220 /* The manufacturer codes are only 1 byte, so just use 1 byte.
221 * This works for any bus width and any FLASH device width.
222 */
223 udelay(100);
224 switch (addr[0] & 0xff) {
225
226 case (uchar)AMD_MANUFACT:
227 info->flash_id = FLASH_MAN_AMD;
228 break;
229
230 case (uchar)INTEL_MANUFACT:
231 info->flash_id = FLASH_MAN_INTEL;
232 break;
233
234 default:
235 info->flash_id = FLASH_UNKNOWN;
236 info->sector_count = 0;
237 info->size = 0;
238 break;
239 }
240
241 /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
242 if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
243
244 case (FPW)AMD_ID_LV065D:
245 info->flash_id += FLASH_AMDLV065D;
246 info->sector_count = 128;
247 info->size = 0x00800000;
248 for( i = 0; i < info->sector_count; i++ )
249 info->start[i] = (ulong)addr + (i * 0x10000);
250 break; /* => 8 or 16 MB */
251
252 default:
253 info->flash_id = FLASH_UNKNOWN;
254 info->sector_count = 0;
255 info->size = 0;
256 return (0); /* => no or unknown flash */
257 }
258
259 /* test for real flash at bank 1 */
260 addr2 = (FPW *)((ulong)addr | 0x800000);
261 if (addr2 != addr &&
262 ((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
263 /* Seems 2 banks are the same space (8Mb chip is installed,
264 * J24 in default position (CS0)). Disable this (first) bank.
265 */
266 info->flash_id = FLASH_UNKNOWN;
267 info->sector_count = 0;
268 info->size = 0;
269 }
270 /* Put FLASH back in read mode */
271 flash_reset(info);
272
273 return (info->size);
274 }
275
276 /*-----------------------------------------------------------------------
277 */
278
279 int flash_erase (flash_info_t *info, int s_first, int s_last)
280 {
281 FPWV *addr;
282 int flag, prot, sect;
283 int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
284 ulong start, now, last;
285 int rcode = 0;
286
287 if ((s_first < 0) || (s_first > s_last)) {
288 if (info->flash_id == FLASH_UNKNOWN) {
289 printf ("- missing\n");
290 } else {
291 printf ("- no sectors to erase\n");
292 }
293 return 1;
294 }
295
296 switch (info->flash_id & FLASH_TYPEMASK) {
297 case FLASH_AMDLV065D:
298 break;
299 case FLASH_UNKNOWN:
300 default:
301 printf ("Can't erase unknown flash type %08lx - aborted\n",
302 info->flash_id);
303 return 1;
304 }
305
306 prot = 0;
307 for (sect=s_first; sect<=s_last; ++sect) {
308 if (info->protect[sect]) {
309 prot++;
310 }
311 }
312
313 if (prot) {
314 printf ("- Warning: %d protected sectors will not be erased!\n",
315 prot);
316 } else {
317 printf ("\n");
318 }
319
320 last = get_timer(0);
321
322 /* Start erase on unprotected sectors */
323 for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
324
325 if (info->protect[sect] != 0) /* protected, skip it */
326 continue;
327
328 /* Disable interrupts which might cause a timeout here */
329 flag = disable_interrupts();
330
331 addr = (FPWV *)(info->start[sect]);
332 if (intel) {
333 *addr = (FPW)0x00500050; /* clear status register */
334 *addr = (FPW)0x00200020; /* erase setup */
335 *addr = (FPW)0x00D000D0; /* erase confirm */
336 }
337 else {
338 /* must be AMD style if not Intel */
339 FPWV *base; /* first address in bank */
340
341 base = (FPWV *)(info->start[0]);
342 base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
343 base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
344 base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
345 base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
346 base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
347 *addr = (FPW)0x00300030; /* erase sector */
348 }
349
350 /* re-enable interrupts if necessary */
351 if (flag)
352 enable_interrupts();
353
354 start = get_timer(0);
355
356 /* wait at least 50us for AMD, 80us for Intel.
357 * Let's wait 1 ms.
358 */
359 udelay (1000);
360
361 while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
362 if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
363 printf ("Timeout\n");
364
365 if (intel) {
366 /* suspend erase */
367 *addr = (FPW)0x00B000B0;
368 }
369
370 flash_reset(info); /* reset to read mode */
371 rcode = 1; /* failed */
372 break;
373 }
374
375 /* show that we're waiting */
376 if ((get_timer(last)) > CFG_HZ) {/* every second */
377 putc ('.');
378 last = get_timer(0);
379 }
380 }
381
382 /* show that we're waiting */
383 if ((get_timer(last)) > CFG_HZ) { /* every second */
384 putc ('.');
385 last = get_timer(0);
386 }
387
388 flash_reset(info); /* reset to read mode */
389 }
390
391 printf (" done\n");
392 return rcode;
393 }
394
395 /*-----------------------------------------------------------------------
396 * Copy memory to flash, returns:
397 * 0 - OK
398 * 1 - write timeout
399 * 2 - Flash not erased
400 */
401 int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
402 {
403 FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
404 int bytes; /* number of bytes to program in current word */
405 int left; /* number of bytes left to program */
406 int i, res;
407
408 for (left = cnt, res = 0;
409 left > 0 && res == 0;
410 addr += sizeof(data), left -= sizeof(data) - bytes) {
411
412 bytes = addr & (sizeof(data) - 1);
413 addr &= ~(sizeof(data) - 1);
414
415 /* combine source and destination data so can program
416 * an entire word of 16 or 32 bits
417 */
418 for (i = 0; i < sizeof(data); i++) {
419 data <<= 8;
420 if (i < bytes || i - bytes >= left )
421 data += *((uchar *)addr + i);
422 else
423 data += *src++;
424 }
425
426 /* write one word to the flash */
427 switch (info->flash_id & FLASH_VENDMASK) {
428 case FLASH_MAN_AMD:
429 res = write_word_amd(info, (FPWV *)addr, data);
430 break;
431 default:
432 /* unknown flash type, error! */
433 printf ("missing or unknown FLASH type\n");
434 res = 1; /* not really a timeout, but gives error */
435 break;
436 }
437 }
438
439 return (res);
440 }
441
442 /*-----------------------------------------------------------------------
443 * Write a word to Flash for AMD FLASH
444 * A word is 16 or 32 bits, whichever the bus width of the flash bank
445 * (not an individual chip) is.
446 *
447 * returns:
448 * 0 - OK
449 * 1 - write timeout
450 * 2 - Flash not erased
451 */
452 static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
453 {
454 ulong start;
455 int flag;
456 int res = 0; /* result, assume success */
457 FPWV *base; /* first address in flash bank */
458
459 /* Check if Flash is (sufficiently) erased */
460 if ((*dest & data) != data) {
461 return (2);
462 }
463
464
465 base = (FPWV *)(info->start[0]);
466
467 /* Disable interrupts which might cause a timeout here */
468 flag = disable_interrupts();
469
470 base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
471 base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
472 base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
473
474 *dest = data; /* start programming the data */
475
476 /* re-enable interrupts if necessary */
477 if (flag)
478 enable_interrupts();
479
480 start = get_timer (0);
481
482 /* data polling for D7 */
483 while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
484 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
485 *dest = (FPW)0x00F000F0; /* reset bank */
486 res = 1;
487 }
488 }
489
490 return (res);
491 }
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