board/ids8247/ids8247.c

   1 /*
   2  * (C) Copyright 2005
   3  * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <ioports.h>
  26 #include <mpc8260.h>
  27
  28 #if defined(CONFIG_OF_LIBFDT)
  29 #include <libfdt.h>
  30 #include <libfdt_env.h>
  31 #include <fdt_support.h>
  32 #endif
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 /*
  37  * I/O Port configuration table
  38  *
  39  * if conf is 1, then that port pin will be configured at boot time
  40  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  41  */
  42
  43 const iop_conf_t iop_conf_tab[4][32] = {
  44
  45     /* Port A configuration */
  46     {   /*            conf ppar psor pdir podr pdat */
  47         /* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 COL */
  48         /* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 CRS */
  49         /* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXER */
  50         /* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXEN */
  51         /* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXDV */
  52         /* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXER */
  53         /* PA25 */ {   0,   0,   0,   0,   1,   0   }, /* 8247_P0 */
  54 #if defined(CONFIG_SOFT_I2C)
  55         /* PA24 */ {   1,   0,   0,   0,   1,   1   }, /* I2C_SDA2 */
  56         /* PA23 */ {   1,   0,   0,   1,   1,   1   }, /* I2C_SCL2 */
  57 #else /* normal I/O port pins */
  58         /* PA24 */ {   0,   0,   0,   1,   0,   0   }, /* PA24 */
  59         /* PA23 */ {   0,   0,   0,   1,   0,   0   }, /* PA23 */
  60 #endif
  61         /* PA22 */ {   0,   0,   0,   0,   1,   0   }, /* SMC2_DCD */
  62         /* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD3 */
  63         /* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD2 */
  64         /* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD1 */
  65         /* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD0 */
  66         /* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD0 */
  67         /* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD1 */
  68         /* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD2 */
  69         /* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD3 */
  70         /* PA13 */ {   0,   0,   0,   1,   1,   0   }, /* SMC2_RTS */
  71         /* PA12 */ {   0,   0,   0,   0,   1,   0   }, /* SMC2_CTS */
  72         /* PA11 */ {   0,   0,   0,   1,   1,   0   }, /* SMC2_DTR */
  73         /* PA10 */ {   0,   0,   0,   0,   1,   0   }, /* SMC2_DSR */
  74         /* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
  75         /* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
  76         /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  77         /* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
  78         /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  79         /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  80         /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  81         /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  82         /* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
  83         /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  84     },
  85
  86     /* Port B configuration */
  87     {   /*            conf ppar psor pdir podr pdat */
  88         /* PB31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  89         /* PB30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  90         /* PB29 */ {   0,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  91         /* PB28 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  92         /* PB27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  93         /* PB26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
  94         /* PB25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
  95         /* PB24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
  96         /* PB23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
  97         /* PB22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
  98         /* PB21 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
  99         /* PB20 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 100         /* PB19 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 101         /* PB18 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
 102         /* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
 103         /* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
 104         /* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
 105         /* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
 106         /* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
 107         /* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
 108         /* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
 109         /* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
 110         /* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
 111         /* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
 112         /* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
 113         /* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
 114         /* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
 115         /* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
 116         /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 117         /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 118         /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 119         /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 120     },
 121
 122     /* Port C */
 123     {   /*            conf ppar psor pdir podr pdat */
 124         /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 125         /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 126         /* PC29 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CLSN */
 127         /* PC28 */ {   0,   1,   1,   0,   0,   0   }, /* SYNC_OUT */
 128         /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* PC27 */
 129         /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 130         /* PC25 */ {   0,   1,   1,   0,   0,   0   }, /* SYNC_IN */
 131         /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 132         /* PC23 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
 133         /* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
 134         /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
 135         /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
 136         /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
 137         /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
 138         /* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 139         /* PC16 */ {   0,   0,   0,   1,   0,   0   }, /* PC16 */
 140         /* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
 141         /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
 142         /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 143         /* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* PC12 */
 144         /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* PC11 */
 145         /* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FCC2 MDC */
 146         /* PC9  */ {   0,   0,   0,   1,   0,   0   }, /* FCC2 MDIO */
 147         /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 148         /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 149         /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 150         /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 151         /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 152         /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 153         /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
 154         /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
 155         /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
 156     },
 157
 158     /* Port D */
 159     {   /*            conf ppar psor pdir podr pdat */
 160         /* PD31 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
 161         /* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
 162         /* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
 163         /* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
 164         /* PD27 */ {   0,   0,   0,   1,   0,   0   }, /* PD27 */
 165         /* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
 166         /* PD25 */ {   0,   1,   0,   0,   0,   0   }, /* SCC3_RX */
 167         /* PD24 */ {   0,   1,   0,   1,   0,   0   }, /* SCC3_TX */
 168         /* PD23 */ {   0,   1,   0,   1,   0,   0   }, /* SCC3_RTS */
 169         /* PD22 */ {   0,   1,   0,   0,   0,   0   }, /* SCC4_RXD */
 170         /* PD21 */ {   0,   1,   0,   1,   0,   0   }, /* SCC4_TXD */
 171         /* PD20 */ {   0,   1,   0,   1,   0,   0   }, /* SCC4_RTS */
 172         /* PD19 */ {   0,   1,   1,   0,   0,   0   }, /* SPI_SEL */
 173         /* PD18 */ {   0,   1,   1,   0,   0,   0   }, /* SPI_CLK */
 174         /* PD17 */ {   0,   1,   1,   0,   0,   0   }, /* SPI_MOSI */
 175         /* PD16 */ {   0,   1,   1,   0,   0,   0   }, /* SPI_MISO */
 176 #if defined(CONFIG_HARD_I2C)
 177         /* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA1 */
 178         /* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL1 */
 179 #else /* normal I/O port pins */
 180         /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* PD15 */
 181         /* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* PD14 */
 182 #endif
 183         /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 184         /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 185         /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 186         /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 187         /* PD9  */ {   0,   0,   0,   0,   0,   0   }, /* PD9 */
 188         /* PD8  */ {   0,   0,   0,   0,   0,   0   }, /* PD8 */
 189         /* PD7  */ {   1,   0,   0,   1,   0,   1   }, /* MII_MDIO */
 190         /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 191         /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 192         /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 193         /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 194         /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 195         /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 196         /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 197     }
 198 };
 199
 200 /* ------------------------------------------------------------------------- */
 201
 202 /* Check Board Identity:
 203  */
 204 int checkboard (void)
 205 {
 206         puts ("Board: IDS 8247\n");
 207         return 0;
 208 }
 209
 210 /* ------------------------------------------------------------------------- */
 211
 212 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 213  *
 214  * This routine performs standard 8260 initialization sequence
 215  * and calculates the available memory size. It may be called
 216  * several times to try different SDRAM configurations on both
 217  * 60x and local buses.
 218  */
 219 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 220                                                   ulong orx, volatile uchar * base)
 221 {
 222         volatile uchar c = 0xff;
 223         volatile uint *sdmr_ptr;
 224         volatile uint *orx_ptr;
 225         ulong maxsize, size;
 226         int i;
 227
 228         /* We must be able to test a location outsize the maximum legal size
 229          * to find out THAT we are outside; but this address still has to be
 230          * mapped by the controller. That means, that the initial mapping has
 231          * to be (at least) twice as large as the maximum expected size.
 232          */
 233         maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
 234
 235         sdmr_ptr = &memctl->memc_psdmr;
 236         orx_ptr = &memctl->memc_or2;
 237
 238         *orx_ptr = orx;
 239
 240         /*
 241          * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 242          *
 243          * "At system reset, initialization software must set up the
 244          *  programmable parameters in the memory controller banks registers
 245          *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
 246          *  system software should execute the following initialization sequence
 247          *  for each SDRAM device.
 248          *
 249          *  1. Issue a PRECHARGE-ALL-BANKS command
 250          *  2. Issue eight CBR REFRESH commands
 251          *  3. Issue a MODE-SET command to initialize the mode register
 252          *
 253          *  The initial commands are executed by setting P/LSDMR[OP] and
 254          *  accessing the SDRAM with a single-byte transaction."
 255          *
 256          * The appropriate BRx/ORx registers have already been set when we
 257          * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 258          */
 259
 260         *sdmr_ptr = sdmr | PSDMR_OP_PREA;
 261         *base = c;
 262
 263         *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
 264         for (i = 0; i < 8; i++)
 265                 *base = c;
 266
 267         *sdmr_ptr = sdmr | PSDMR_OP_MRW;
 268         *(base + CONFIG_SYS_MRS_OFFS) = c;      /* setting MR on address lines */
 269
 270         *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 271         *base = c;
 272
 273         size = get_ram_size((long *)base, maxsize);
 274         *orx_ptr = orx | ~(size - 1);
 275
 276         return (size);
 277 }
 278
 279 phys_size_t initdram (int board_type)
 280 {
 281         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 282         volatile memctl8260_t *memctl = &immap->im_memctl;
 283
 284         long psize, lsize;
 285
 286         psize = 16 * 1024 * 1024;
 287         lsize = 0;
 288
 289         memctl->memc_psrt = CONFIG_SYS_PSRT;
 290         memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 291
 292 #ifndef CONFIG_SYS_RAMBOOT
 293         /* 60x SDRAM setup:
 294          */
 295         psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
 296                                                   (uchar *) CONFIG_SYS_SDRAM_BASE);
 297 #endif /* CONFIG_SYS_RAMBOOT */
 298
 299         icache_enable ();
 300
 301         return (psize);
 302 }
 303
 304 int misc_init_r (void)
 305 {
 306         gd->bd->bi_flashstart = 0xff800000;
 307 }
 308
 309 #if defined(CONFIG_CMD_NAND)
 310 extern ulong
 311 nand_probe (ulong physadr);
 312
 313 void
 314 nand_init (void)
 315 {
 316         ulong totlen = 0;
 317
 318         debug ("Probing at 0x%.8x\n", CONFIG_SYS_NAND0_BASE);
 319         totlen += nand_probe (CONFIG_SYS_NAND0_BASE);
 320
 321         printf ("%4lu MB\n", totlen >>20);
 322 }
 323
 324 #endif  /* CONFIG_CMD_NAND */
 325
 326 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 327 /*
 328  * update "memory" property in the blob
 329  */
 330 void ft_blob_update(void *blob, bd_t *bd)
 331 {
 332         int ret;
 333
 334         ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 335
 336         if (ret < 0) {
 337                 printf("ft_blob_update(): cannot set /memory/reg "
 338                         "property err:%s\n", fdt_strerror(ret));
 339         }
 340 }
 341
 342 void ft_board_setup(void *blob, bd_t *bd)
 343 {
 344         ft_cpu_setup( blob, bd);
 345         ft_blob_update(blob, bd);
 346 }
 347 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */