board/incaip/lowlevel_init.S

   1 /*
   2  *  Memory sub-system initialization code for INCA-IP development board.
   3  *
   4  *  Copyright (c) 2003  Wolfgang Denk <wd@denx.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <config.h>
  10 #include <asm/regdef.h>
  11
  12
  13 #define EBU_MODUL_BASE          0xB8000200
  14 #define EBU_CLC(value)          0x0000(value)
  15 #define EBU_CON(value)          0x0010(value)
  16 #define EBU_ADDSEL0(value)      0x0020(value)
  17 #define EBU_ADDSEL1(value)      0x0024(value)
  18 #define EBU_ADDSEL2(value)      0x0028(value)
  19 #define EBU_BUSCON0(value)      0x0060(value)
  20 #define EBU_BUSCON1(value)      0x0064(value)
  21 #define EBU_BUSCON2(value)      0x0068(value)
  22
  23 #define MC_MODUL_BASE           0xBF800000
  24 #define MC_ERRCAUSE(value)      0x0100(value)
  25 #define MC_ERRADDR(value)       0x0108(value)
  26 #define MC_IOGP(value)          0x0800(value)
  27 #define MC_SELFRFSH(value)      0x0A00(value)
  28 #define MC_CTRLENA(value)       0x1000(value)
  29 #define MC_MRSCODE(value)       0x1008(value)
  30 #define MC_CFGDW(value)         0x1010(value)
  31 #define MC_CFGPB0(value)        0x1018(value)
  32 #define MC_LATENCY(value)       0x1038(value)
  33 #define MC_TREFRESH(value)      0x1040(value)
  34
  35 #define CGU_MODUL_BASE          0xBF107000
  36 #define CGU_PLL1CR(value)       0x0008(value)
  37 #define CGU_DIVCR(value)        0x0010(value)
  38 #define CGU_MUXCR(value)        0x0014(value)
  39 #define CGU_PLL1SR(value)       0x000C(value)
  40
  41         .set    noreorder
  42
  43
  44 /*
  45  * void ebu_init(long)
  46  *
  47  * a0 has the clock value we are going to run at
  48  */
  49         .globl  ebu_init
  50         .ent    ebu_init
  51 ebu_init:
  52 __ebu_init:
  53
  54         li      t1, EBU_MODUL_BASE
  55         li      t2, 0xA0000041
  56         sw      t2, EBU_ADDSEL0(t1)
  57         li      t2, 0xA0800041
  58         sw      t2, EBU_ADDSEL2(t1)
  59         li      t2, 0xBE0000F1
  60         sw      t2, EBU_ADDSEL1(t1)
  61
  62         li      t3, 100000000
  63         beq     a0, t3, 1f
  64         nop
  65         li      t3, 133000000
  66         beq     a0, t3, 2f
  67         nop
  68         li      t3, 150000000
  69         beq     a0, t3, 2f
  70         nop
  71         b       3f
  72         nop
  73
  74         /* 100 MHz */
  75 1:
  76         li      t2, 0x8841417D
  77         sw      t2, EBU_BUSCON0(t1)
  78         sw      t2, EBU_BUSCON2(t1)
  79         li      t2, 0x684142BD
  80         b       3f
  81         sw      t2, EBU_BUSCON1(t1)     /* delay slot */
  82
  83         /* 133 or 150 MHz */
  84 2:
  85         li      t2, 0x8841417E
  86         sw      t2, EBU_BUSCON0(t1)
  87         sw      t2, EBU_BUSCON2(t1)
  88         li      t2, 0x684143FD
  89         sw      t2, EBU_BUSCON1(t1)
  90 3:
  91         jr      ra
  92         nop
  93
  94         .end    ebu_init
  95
  96
  97 /*
  98  * void cgu_init(long)
  99  *
 100  * a0 has the clock value
 101  */
 102         .globl  cgu_init
 103         .ent    cgu_init
 104 cgu_init:
 105 __cgu_init:
 106
 107         li      t1, CGU_MODUL_BASE
 108
 109         li      t3, 100000000
 110         beq     a0, t3, 1f
 111         nop
 112         li      t3, 133000000
 113         beq     a0, t3, 2f
 114         nop
 115         li      t3, 150000000
 116         beq     a0, t3, 3f
 117         nop
 118         b       5f
 119         nop
 120
 121         /* 100 MHz clock */
 122 1:
 123         li      t2, 0x80000014
 124         sw      t2, CGU_DIVCR(t1)
 125         li      t2, 0x80000000
 126         sw      t2, CGU_MUXCR(t1)
 127         li      t2, 0x800B0001
 128         b       5f
 129         sw      t2, CGU_PLL1CR(t1)      /* delay slot */
 130
 131         /* 133 MHz clock */
 132 2:
 133         li      t2, 0x80000054
 134         sw      t2, CGU_DIVCR(t1)
 135         li      t2, 0x80000000
 136         sw      t2, CGU_MUXCR(t1)
 137         li      t2, 0x800B0001
 138         b       5f
 139         sw      t2, CGU_PLL1CR(t1)      /* delay slot */
 140
 141         /* 150 MHz clock */
 142 3:
 143         li      t2, 0x80000017
 144         sw      t2, CGU_DIVCR(t1)
 145         li      t2, 0xC00B0001
 146         sw      t2, CGU_PLL1CR(t1)
 147         li      t3, 0x80000000
 148 4:
 149         lw      t2, CGU_PLL1SR(t1)
 150         and     t2, t2, t3
 151         beq     t2, zero, 4b
 152         nop
 153         li      t2, 0x80000001
 154         sw      t2, CGU_MUXCR(t1)
 155 5:
 156         jr      ra
 157         nop
 158
 159         .end    cgu_init
 160
 161
 162 /*
 163  * void sdram_init(long)
 164  *
 165  * a0 has the clock value
 166  */
 167         .globl  sdram_init
 168         .ent    sdram_init
 169 sdram_init:
 170 __sdram_init:
 171
 172         li      t1, MC_MODUL_BASE
 173
 174 #if 0
 175         /* Disable memory controller before changing any of its registers */
 176         sw      zero, MC_CTRLENA(t1)
 177 #endif
 178
 179         li      t2, 100000000
 180         beq     a0, t2, 1f
 181         nop
 182         li      t2, 133000000
 183         beq     a0, t2, 2f
 184         nop
 185         li      t2, 150000000
 186         beq     a0, t2, 3f
 187         nop
 188         b       5f
 189         nop
 190
 191         /* 100 MHz clock */
 192 1:
 193         /* Set clock ratio (clkrat=1:1, rddel=3) */
 194         li      t2, 0x00000003
 195         sw      t2, MC_IOGP(t1)
 196
 197         /* Set sdram refresh rate (4K/64ms @ 100MHz) */
 198         li      t2, 0x0000061A
 199         b       4f
 200         sw      t2, MC_TREFRESH(t1)
 201
 202         /* 133 MHz clock */
 203 2:
 204         /* Set clock ratio (clkrat=1:1, rddel=3) */
 205         li      t2, 0x00000003
 206         sw      t2, MC_IOGP(t1)
 207
 208         /* Set sdram refresh rate (4K/64ms @ 133MHz) */
 209         li      t2, 0x00000822
 210         b       4f
 211         sw      t2, MC_TREFRESH(t1)
 212
 213         /* 150 MHz clock */
 214 3:
 215         /* Set clock ratio (clkrat=3:2, rddel=4) */
 216         li      t2, 0x00000014
 217         sw      t2, MC_IOGP(t1)
 218
 219         /* Set sdram refresh rate (4K/64ms @ 150MHz) */
 220         li      t2, 0x00000927
 221         sw      t2, MC_TREFRESH(t1)
 222
 223 4:
 224         /* Clear Error log registers */
 225         sw      zero, MC_ERRCAUSE(t1)
 226         sw      zero, MC_ERRADDR(t1)
 227
 228         /* Clear Power-down registers */
 229         sw      zero, MC_SELFRFSH(t1)
 230
 231         /* Set CAS Latency */
 232         li      t2, 0x00000020          /* CL = 2 */
 233         sw      t2, MC_MRSCODE(t1)
 234
 235         /* Set word width to 16 bit */
 236         li      t2, 0x2
 237         sw      t2, MC_CFGDW(t1)
 238
 239         /* Set CS0 to SDRAM parameters */
 240         li      t2, 0x000014C9
 241         sw      t2, MC_CFGPB0(t1)
 242
 243         /* Set SDRAM latency parameters */
 244         li      t2, 0x00026325          /* BC PC100 */
 245         sw      t2, MC_LATENCY(t1)
 246
 247 5:
 248         /* Finally enable the controller */
 249         li      t2, 0x00000001
 250         sw      t2, MC_CTRLENA(t1)
 251
 252         jr      ra
 253         nop
 254
 255         .end    sdram_init
 256
 257
 258         .globl  lowlevel_init
 259         .ent    lowlevel_init
 260 lowlevel_init:
 261
 262         /* Disable Watchdog.
 263          */
 264         la      t9, disable_incaip_wdt
 265         jalr    t9
 266         nop
 267
 268         /* EBU, CGU and SDRAM Initialization.
 269          */
 270         li      a0, CONFIG_CPU_CLOCK_RATE
 271         move    t0, ra
 272
 273         /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
 274          * modify t0 and a0.
 275          */
 276         bal     __cgu_init
 277         nop
 278         bal     __ebu_init
 279         nop
 280         bal     __sdram_init
 281         nop
 282         move    ra, t0
 283
 284         jr      ra
 285         nop
 286
 287         .end    lowlevel_init