board/ivm/ivm.c

   1 /*
   2  * (C) Copyright 2000, 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <mpc8xx.h>
  27 #include <commproc.h>
  28
  29 #ifdef CONFIG_STATUS_LED
  30 # include <status_led.h>
  31 #endif
  32
  33 /* ------------------------------------------------------------------------- */
  34
  35 static long int dram_size (long int, long int *, long int);
  36
  37 /* ------------------------------------------------------------------------- */
  38
  39 #define _NOT_USED_      0xFFFFFFFF
  40
  41 /*
  42  * 50 MHz SHARC access using UPM A
  43  */
  44 const uint sharc_table[] = {
  45         /*
  46          * Single Read. (Offset 0 in UPM RAM)
  47          */
  48         0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
  49         0xFFFFEC05,             /* last */
  50         _NOT_USED_, _NOT_USED_, _NOT_USED_,
  51         /*
  52          * Burst Read. (Offset 8 in UPM RAM)
  53          */
  54         /* last */
  55         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  56         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  57         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  58         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  59         /*
  60          * Single Write. (Offset 18 in UPM RAM)
  61          */
  62         0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
  63         0xFFFFEC05,             /* last */
  64         _NOT_USED_, _NOT_USED_, _NOT_USED_,
  65         /*
  66          * Burst Write. (Offset 20 in UPM RAM)
  67          */
  68         /* last */
  69         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  70         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  71         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  72         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  73         /*
  74          * Refresh  (Offset 30 in UPM RAM)
  75          */
  76         /* last */
  77         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  78         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  79         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  80         /*
  81          * Exception. (Offset 3c in UPM RAM)
  82          */
  83         0x7FFFFC07,             /* last */
  84         _NOT_USED_, _NOT_USED_, _NOT_USED_,
  85 };
  86
  87
  88 /*
  89  * 50 MHz SDRAM access using UPM B
  90  */
  91 const uint sdram_table[] = {
  92         /*
  93          * Single Read. (Offset 0 in UPM RAM)
  94          */
  95         0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */
  96         _NOT_USED_,
  97         /*
  98          * SDRAM Initialization (offset 5 in UPM RAM)
  99          *
 100          * This is no UPM entry point. The following definition uses
 101          * the remaining space to establish an initialization
 102          * sequence, which is executed by a RUN command.
 103          *
 104          */
 105         0x1FF77C35, 0xEFEABC34, 0x1FB57C35,     /* last */
 106         /*
 107          * Burst Read. (Offset 8 in UPM RAM)
 108          */
 109         0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
 110         0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45,     /* last */
 111         _NOT_USED_,
 112         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 113         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 114         /*
 115          * Single Write. (Offset 18 in UPM RAM)
 116          */
 117         0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */
 118         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 119         /*
 120          * Burst Write. (Offset 20 in UPM RAM)
 121          */
 122         0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
 123         0xE1BBBC04, 0x1FF77C45, /* last */
 124         _NOT_USED_, _NOT_USED_,
 125         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 126         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 127         /*
 128          * Refresh  (Offset 30 in UPM RAM)
 129          */
 130         0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
 131         0xFFFFFC05,             /* last */
 132         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 133         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 134         /*
 135          * Exception. (Offset 3c in UPM RAM)
 136          */
 137         0x7FFFFC07,             /* last */
 138         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 139 };
 140
 141 /* ------------------------------------------------------------------------- */
 142
 143
 144 /*
 145  * Check Board Identity:
 146  *
 147  */
 148
 149 int checkboard (void)
 150 {
 151 #ifdef CONFIG_IVMS8
 152         puts ("Board: IVMS8\n");
 153 #endif
 154 #ifdef CONFIG_IVML24
 155         puts ("Board: IVM-L8/24\n");
 156 #endif
 157         return (0);
 158 }
 159
 160 /* ------------------------------------------------------------------------- */
 161
 162 phys_size_t initdram (int board_type)
 163 {
 164         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 165         volatile memctl8xx_t *memctl = &immr->im_memctl;
 166         long int size_b0;
 167
 168         /* enable SDRAM clock ("switch on" SDRAM) */
 169         immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_SDRAM_CLKE);   /* GPIO */
 170         immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_SDRAM_CLKE);   /* active output */
 171         immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_SDRAM_CLKE;      /* output */
 172         immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_SDRAM_CLKE;      /* assert SDRAM CLKE */
 173         udelay (1);
 174
 175         /*
 176          * Map controller bank 1 for ELIC SACCO
 177          */
 178         memctl->memc_or1 = CONFIG_SYS_OR1;
 179         memctl->memc_br1 = CONFIG_SYS_BR1;
 180
 181         /*
 182          * Map controller bank 2 for ELIC EPIC
 183          */
 184         memctl->memc_or2 = CONFIG_SYS_OR2;
 185         memctl->memc_br2 = CONFIG_SYS_BR2;
 186
 187         /*
 188          * Configure UPMA for SHARC
 189          */
 190         upmconfig (UPMA, (uint *) sharc_table,
 191                    sizeof (sharc_table) / sizeof (uint));
 192
 193 #if defined(CONFIG_IVML24)
 194         /*
 195          * Map controller bank 4 for HDLC Address space
 196          */
 197         memctl->memc_or4 = CONFIG_SYS_OR4;
 198         memctl->memc_br4 = CONFIG_SYS_BR4;
 199 #endif
 200
 201         /*
 202          * Map controller bank 5 for SHARC
 203          */
 204         memctl->memc_or5 = CONFIG_SYS_OR5;
 205         memctl->memc_br5 = CONFIG_SYS_BR5;
 206
 207         memctl->memc_mamr = 0x00001000;
 208
 209         /*
 210          * Configure UPMB for SDRAM
 211          */
 212         upmconfig (UPMB, (uint *) sdram_table,
 213                    sizeof (sdram_table) / sizeof (uint));
 214
 215         memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
 216
 217         memctl->memc_mar = 0x00000088;
 218
 219         /*
 220          * Map controller bank 3 to the SDRAM bank at preliminary address.
 221          */
 222         memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 223         memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 224
 225         memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;       /* refresh not enabled yet */
 226
 227         udelay (200);
 228         memctl->memc_mcr = 0x80806105;  /* precharge */
 229         udelay (1);
 230         memctl->memc_mcr = 0x80806106;  /* load mode register */
 231         udelay (1);
 232         memctl->memc_mcr = 0x80806130;  /* autorefresh */
 233         udelay (1);
 234         memctl->memc_mcr = 0x80806130;  /* autorefresh */
 235         udelay (1);
 236         memctl->memc_mcr = 0x80806130;  /* autorefresh */
 237         udelay (1);
 238         memctl->memc_mcr = 0x80806130;  /* autorefresh */
 239         udelay (1);
 240         memctl->memc_mcr = 0x80806130;  /* autorefresh */
 241         udelay (1);
 242         memctl->memc_mcr = 0x80806130;  /* autorefresh */
 243         udelay (1);
 244         memctl->memc_mcr = 0x80806130;  /* autorefresh */
 245         udelay (1);
 246         memctl->memc_mcr = 0x80806130;  /* autorefresh */
 247
 248         memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
 249
 250         /*
 251          * Check Bank 0 Memory Size for re-configuration
 252          */
 253         size_b0 =
 254                 dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
 255                            SDRAM_MAX_SIZE);
 256
 257         memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
 258
 259         return (size_b0);
 260 }
 261
 262 /* ------------------------------------------------------------------------- */
 263
 264 /*
 265  * Check memory range for valid RAM. A simple memory test determines
 266  * the actually available RAM size between addresses `base' and
 267  * `base + maxsize'. Some (not all) hardware errors are detected:
 268  * - short between address lines
 269  * - short between data lines
 270  */
 271
 272 static long int dram_size (long int mamr_value, long int *base,
 273                            long int maxsize)
 274 {
 275         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 276         volatile memctl8xx_t *memctl = &immr->im_memctl;
 277
 278         memctl->memc_mbmr = mamr_value;
 279
 280         return (get_ram_size (base, maxsize));
 281 }
 282
 283 /* ------------------------------------------------------------------------- */
 284
 285 void reset_phy (void)
 286 {
 287         immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 288
 289         /* De-assert Ethernet Powerdown */
 290         immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_ETH_POWERDOWN);        /* GPIO */
 291         immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_ETH_POWERDOWN);        /* active output */
 292         immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_ETH_POWERDOWN;   /* output */
 293         immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN);        /* Enable PHY power */
 294         udelay (1000);
 295
 296         /*
 297          * RESET is implemented by a positive pulse of at least 1 us
 298          * at the reset pin.
 299          *
 300          * Configure RESET pins for NS DP83843 PHY, and RESET chip.
 301          *
 302          * Note: The RESET pin is high active, but there is an
 303          *       inverter on the SPD823TS board...
 304          */
 305         immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_ETH_RESET);
 306         immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_ETH_RESET;
 307         /* assert RESET signal of PHY */
 308         immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_ETH_RESET);
 309         udelay (10);
 310         /* de-assert RESET signal of PHY */
 311         immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_ETH_RESET;
 312         udelay (10);
 313 }
 314
 315 /* ------------------------------------------------------------------------- */
 316
 317 void show_boot_progress (int status)
 318 {
 319 #if defined(CONFIG_STATUS_LED)
 320 # if defined(STATUS_LED_YELLOW)
 321         status_led_set (STATUS_LED_YELLOW,
 322                         (status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
 323 # endif /* STATUS_LED_YELLOW */
 324 # if defined(STATUS_LED_BOOT)
 325         if (status == 6)
 326                 status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
 327 # endif /* STATUS_LED_BOOT */
 328 #endif /* CONFIG_STATUS_LED */
 329 }
 330
 331 /* ------------------------------------------------------------------------- */
 332
 333 void ide_set_reset (int on)
 334 {
 335         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 336
 337         /*
 338          * Configure PC for IDE Reset Pin
 339          */
 340         if (on) {               /* assert RESET */
 341                 immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
 342         } else {                /* release RESET */
 343                 immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
 344         }
 345
 346         /* program port pin as GPIO output */
 347         immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
 348         immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
 349         immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
 350 }
 351
 352 /* ------------------------------------------------------------------------- */