board/keymile/km82xx/km82xx.c

   1 /*
   2  * (C) Copyright 2007 - 2008
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <mpc8260.h>
  10 #include <ioports.h>
  11 #include <malloc.h>
  12 #include <asm/io.h>
  13
  14 #include <libfdt.h>
  15 #include <i2c.h>
  16 #include "../common/common.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  21
  22 /*
  23  * I/O Port configuration table
  24  *
  25  * if conf is 1, then that port pin will be configured at boot time
  26  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  27  */
  28 const iop_conf_t iop_conf_tab[4][32] = {
  29
  30         /* Port A */
  31         {       /*            conf      ppar psor pdir podr pdat */
  32                 { 0,             0,   0,   0,   0,   0 }, /* PA31            */
  33                 { 0,             0,   0,   0,   0,   0 }, /* PA30            */
  34                 { 0,             0,   0,   0,   0,   0 }, /* PA29            */
  35                 { 0,             0,   0,   0,   0,   0 }, /* PA28            */
  36                 { 0,             0,   0,   0,   0,   0 }, /* PA27            */
  37                 { 0,             0,   0,   0,   0,   0 }, /* PA26            */
  38                 { 0,             0,   0,   0,   0,   0 }, /* PA25            */
  39                 { 0,             0,   0,   0,   0,   0 }, /* PA24            */
  40                 { 0,             0,   0,   0,   0,   0 }, /* PA23            */
  41                 { 0,             0,   0,   0,   0,   0 }, /* PA22            */
  42                 { 0,             0,   0,   0,   0,   0 }, /* PA21            */
  43                 { 0,             0,   0,   0,   0,   0 }, /* PA20            */
  44                 { 0,             0,   0,   0,   0,   0 }, /* PA19            */
  45                 { 0,             0,   0,   0,   0,   0 }, /* PA18            */
  46                 { 0,             0,   0,   0,   0,   0 }, /* PA17            */
  47                 { 0,             0,   0,   0,   0,   0 }, /* PA16            */
  48                 { 0,             0,   0,   0,   0,   0 }, /* PA15            */
  49                 { 0,             0,   0,   0,   0,   0 }, /* PA14            */
  50                 { 0,             0,   0,   0,   0,   0 }, /* PA13            */
  51                 { 0,             0,   0,   0,   0,   0 }, /* PA12            */
  52                 { 0,             0,   0,   0,   0,   0 }, /* PA11            */
  53                 { 0,             0,   0,   0,   0,   0 }, /* PA10            */
  54                 { 1,             1,   0,   1,   0,   0 }, /* PA9 SMC2 TxD    */
  55                 { 1,             1,   0,   0,   0,   0 }, /* PA8 SMC2 RxD    */
  56                 { 0,             0,   0,   0,   0,   0 }, /* PA7             */
  57                 { 0,             0,   0,   0,   0,   0 }, /* PA6             */
  58                 { 0,             0,   0,   0,   0,   0 }, /* PA5             */
  59                 { 0,             0,   0,   0,   0,   0 }, /* PA4             */
  60                 { 0,             0,   0,   0,   0,   0 }, /* PA3             */
  61                 { 0,             0,   0,   0,   0,   0 }, /* PA2             */
  62                 { 0,             0,   0,   0,   0,   0 }, /* PA1             */
  63                 { 0,             0,   0,   0,   0,   0 }  /* PA0             */
  64         },
  65
  66         /* Port B */
  67         {       /*            conf      ppar psor pdir podr pdat */
  68                 { 0,             0,   0,   0,   0,   0 }, /* PB31            */
  69                 { 0,             0,   0,   0,   0,   0 }, /* PB30            */
  70                 { 0,             0,   0,   0,   0,   0 }, /* PB29            */
  71                 { 0,             0,   0,   0,   0,   0 }, /* PB28            */
  72                 { 0,             0,   0,   0,   0,   0 }, /* PB27            */
  73                 { 0,             0,   0,   0,   0,   0 }, /* PB26            */
  74                 { 0,             0,   0,   0,   0,   0 }, /* PB25            */
  75                 { 0,             0,   0,   0,   0,   0 }, /* PB24            */
  76                 { 0,             0,   0,   0,   0,   0 }, /* PB23            */
  77                 { 0,             0,   0,   0,   0,   0 }, /* PB22            */
  78                 { 0,             0,   0,   0,   0,   0 }, /* PB21            */
  79                 { 0,             0,   0,   0,   0,   0 }, /* PB20            */
  80                 { 0,             0,   0,   0,   0,   0 }, /* PB19            */
  81                 { 0,             0,   0,   0,   0,   0 }, /* PB18            */
  82                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  83                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  84                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  85                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  86                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  87                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  88                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  89                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  90                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  91                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  92                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  93                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  94                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  95                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  96                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  97                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  98                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  99                 { 0,             0,   0,   0,   0,   0 }  /* non-existent    */
 100         },
 101
 102         /* Port C */
 103         {       /*            conf      ppar psor pdir podr pdat */
 104                 { 0,             0,   0,   0,   0,   0 }, /* PC31            */
 105                 { 0,             0,   0,   0,   0,   0 }, /* PC30            */
 106                 { 0,             0,   0,   0,   0,   0 }, /* PC29            */
 107                 { 0,             0,   0,   0,   0,   0 }, /* PC28            */
 108                 { 0,             0,   0,   0,   0,   0 }, /* PC27            */
 109                 { 0,             0,   0,   0,   0,   0 }, /* PC26            */
 110                 { 1,             1,   0,   0,   0,   0 }, /* PC25 RxClk      */
 111                 { 1,             1,   0,   0,   0,   0 }, /* PC24 TxClk      */
 112                 { 0,             0,   0,   0,   0,   0 }, /* PC23            */
 113                 { 0,             0,   0,   0,   0,   0 }, /* PC22            */
 114                 { 0,             0,   0,   0,   0,   0 }, /* PC21            */
 115                 { 0,             0,   0,   0,   0,   0 }, /* PC20            */
 116                 { 0,             0,   0,   0,   0,   0 }, /* PC19            */
 117                 { 0,             0,   0,   0,   0,   0 }, /* PC18            */
 118                 { 0,             0,   0,   0,   0,   0 }, /* PC17            */
 119                 { 0,             0,   0,   0,   0,   0 }, /* PC16            */
 120                 { 0,             0,   0,   0,   0,   0 }, /* PC15            */
 121                 { 0,             0,   0,   0,   0,   0 }, /* PC14            */
 122                 { 0,             0,   0,   0,   0,   0 }, /* PC13            */
 123                 { 0,             0,   0,   0,   0,   0 }, /* PC12            */
 124                 { 0,             0,   0,   0,   0,   0 }, /* PC11            */
 125                 { 0,             0,   0,   0,   0,   0 }, /* PC10            */
 126                 { 1,             1,   0,   0,   0,   0 }, /* PC9  SCC4: CTS  */
 127                 { 1,             1,   0,   0,   0,   0 }, /* PC8  SCC4: CD   */
 128                 { 0,             0,   0,   0,   0,   0 }, /* PC7             */
 129                 { 0,             0,   0,   0,   0,   0 }, /* PC6             */
 130                 { 0,             0,   0,   0,   0,   0 }, /* PC5             */
 131                 { 0,             0,   0,   0,   0,   0 }, /* PC4             */
 132                 { 0,             0,   0,   0,   0,   0 }, /* PC3             */
 133                 { 0,             0,   0,   0,   0,   0 }, /* PC2             */
 134                 { 0,             0,   0,   0,   0,   0 }, /* PC1             */
 135                 { 0,             0,   0,   0,   0,   0 }, /* PC0             */
 136         },
 137
 138         /* Port D */
 139         {       /*            conf      ppar psor pdir podr pdat */
 140                 { 0,             0,   0,   0,   0,   0 }, /* PD31            */
 141                 { 0,             0,   0,   0,   0,   0 }, /* PD30            */
 142                 { 0,             0,   0,   0,   0,   0 }, /* PD29            */
 143                 { 0,             0,   0,   0,   0,   0 }, /* PD28            */
 144                 { 0,             0,   0,   0,   0,   0 }, /* PD27            */
 145                 { 0,             0,   0,   0,   0,   0 }, /* PD26            */
 146                 { 0,             0,   0,   0,   0,   0 }, /* PD25            */
 147                 { 0,             0,   0,   0,   0,   0 }, /* PD24            */
 148                 { 0,             0,   0,   0,   0,   0 }, /* PD23            */
 149                 { 1,             1,   0,   0,   0,   0 }, /* PD22 SCC4: RXD  */
 150                 { 1,             1,   0,   1,   0,   0 }, /* PD21 SCC4: TXD  */
 151                 { 1,             1,   0,   1,   0,   0 }, /* PD20 SCC4: RTS  */
 152                 { 0,             0,   0,   0,   0,   0 }, /* PD19            */
 153                 { 0,             0,   0,   0,   0,   0 }, /* PD18            */
 154                 { 0,             0,   0,   0,   0,   0 }, /* PD17            */
 155                 { 0,             0,   0,   0,   0,   0 }, /* PD16            */
 156                 { 1,             0,   0,   0,   1,   1 }, /* PD15            */
 157                 { 1,             0,   0,   1,   1,   1 }, /* PD14            */
 158                 { 0,             0,   0,   0,   0,   0 }, /* PD13            */
 159                 { 0,             0,   0,   0,   0,   0 }, /* PD12            */
 160                 { 0,             0,   0,   0,   0,   0 }, /* PD11            */
 161                 { 0,             0,   0,   0,   0,   0 }, /* PD10            */
 162                 { 0,             0,   0,   0,   0,   0 }, /* PD9             */
 163                 { 0,             0,   0,   0,   0,   0 }, /* PD8             */
 164                 { 0,             0,   0,   0,   0,   0 }, /* PD7             */
 165                 { 0,             0,   0,   0,   0,   0 }, /* PD6             */
 166                 { 0,             0,   0,   0,   0,   0 }, /* PD5             */
 167                 { 0,             0,   0,   0,   0,   0 }, /* PD4             */
 168                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 169                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 170                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 171                 { 0,             0,   0,   0,   0,   0 }  /* non-existent    */
 172         }
 173 };
 174
 175 /*
 176  * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 177  *
 178  * This routine performs standard 8260 initialization sequence
 179  * and calculates the available memory size. It may be called
 180  * several times to try different SDRAM configurations on both
 181  * 60x and local buses.
 182  */
 183 static long int try_init(memctl8260_t *memctl, ulong sdmr,
 184                                   ulong orx, uchar *base)
 185 {
 186         uchar c = 0xff;
 187         ulong maxsize, size;
 188         int i;
 189
 190         /*
 191          * We must be able to test a location outsize the maximum legal size
 192          * to find out THAT we are outside; but this address still has to be
 193          * mapped by the controller. That means, that the initial mapping has
 194          * to be (at least) twice as large as the maximum expected size.
 195          */
 196         maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
 197
 198         out_be32(&memctl->memc_or1, orx);
 199
 200         /*
 201          * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 202          *
 203          * "At system reset, initialization software must set up the
 204          *  programmable parameters in the memory controller banks registers
 205          *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
 206          *  system software should execute the following initialization sequence
 207          *  for each SDRAM device.
 208          *
 209          *  1. Issue a PRECHARGE-ALL-BANKS command
 210          *  2. Issue eight CBR REFRESH commands
 211          *  3. Issue a MODE-SET command to initialize the mode register
 212          *
 213          *  The initial commands are executed by setting P/LSDMR[OP] and
 214          *  accessing the SDRAM with a single-byte transaction."
 215          *
 216          * The appropriate BRx/ORx registers have already been set when we
 217          * get here. The SDRAM can be accessed at the address
 218          * CONFIG_SYS_SDRAM_BASE.
 219          */
 220
 221         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
 222         out_8(base, c);
 223
 224         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
 225         for (i = 0; i < 8; i++)
 226                 out_8(base, c);
 227
 228         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
 229         /* setting MR on address lines */
 230         out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
 231
 232         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
 233         out_8(base, c);
 234
 235         size = get_ram_size((long *)base, maxsize);
 236         out_be32(&memctl->memc_or1, orx | ~(size - 1));
 237
 238         return size;
 239 }
 240
 241 #ifdef CONFIG_SYS_SDRAM_LIST
 242
 243 /*
 244  * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM
 245  * configurations therein (should be from high to lower) to find the
 246  * one actually matching the current configuration.
 247  * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are
 248  * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST
 249  * (defined as the initialization value for the array of struct sdram_conf_s)
 250  * will then be ORed with such base values.
 251  */
 252
 253 struct sdram_conf_s {
 254         ulong size;
 255         int or1;
 256         int psdmr;
 257 };
 258
 259 static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST;
 260
 261 static long probe_sdram(memctl8260_t *memctl)
 262 {
 263         int n = 0;
 264         long psize = 0;
 265
 266         for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) {
 267                 psize = try_init(memctl,
 268                         CONFIG_SYS_PSDMR | sdram_conf[n].psdmr,
 269                         CONFIG_SYS_OR1 | sdram_conf[n].or1,
 270                         (uchar *) CONFIG_SYS_SDRAM_BASE);
 271                 debug("Probing %ld bytes returned %ld\n",
 272                         sdram_conf[n].size, psize);
 273                 if (psize == sdram_conf[n].size)
 274                         break;
 275         }
 276         return psize;
 277 }
 278
 279 #else /* CONFIG_SYS_SDRAM_LIST */
 280
 281 static long probe_sdram(memctl8260_t *memctl)
 282 {
 283         return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
 284                                         (uchar *) CONFIG_SYS_SDRAM_BASE);
 285 }
 286 #endif /* CONFIG_SYS_SDRAM_LIST */
 287
 288
 289 int dram_init(void)
 290 {
 291         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 292         memctl8260_t *memctl = &immap->im_memctl;
 293
 294         long psize;
 295
 296         out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
 297         out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
 298
 299         /* 60x SDRAM setup:
 300          */
 301         psize = probe_sdram(memctl);
 302
 303         icache_enable();
 304
 305         gd->ram_size = psize;
 306
 307         return 0;
 308 }
 309
 310 int checkboard(void)
 311 {
 312 #if defined(CONFIG_MGCOGE)
 313         puts("Board: Keymile mgcoge");
 314 #else
 315         puts("Board: Keymile mgcoge3ne");
 316 #endif
 317         if (ethernet_present())
 318                 puts(" with PIGGY.");
 319         puts("\n");
 320         return 0;
 321 }
 322
 323 int last_stage_init(void)
 324 {
 325         struct bfticu_iomap *base =
 326                 (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE;
 327         u8 dip_switch;
 328
 329         dip_switch = in_8(&base->mswitch);
 330         dip_switch &= BFTICU_DIPSWITCH_MASK;
 331         /* dip switch 'full reset' or 'db erase' or 'Local mgmt IP' or any */
 332         if (dip_switch != 0) {
 333                 /* start bootloader */
 334                 puts("DIP:   Enabled\n");
 335                 setenv("actual_bank", "0");
 336         }
 337         set_km_env();
 338         return 0;
 339 }
 340
 341 #ifdef CONFIG_MGCOGE3NE
 342 static void set_pin(int state, unsigned long mask, int port);
 343
 344 /*
 345  * For mgcoge3ne boards, the mgcoge3un control is controlled from
 346  * a GPIO line on the PPC CPU. If bobcatreset is set the line
 347  * will toggle once what forces the mgocge3un part to restart
 348  * immediately.
 349  */
 350 static void handle_mgcoge3un_reset(void)
 351 {
 352         char *bobcatreset = getenv("bobcatreset");
 353         if (bobcatreset) {
 354                 if (strcmp(bobcatreset, "true") == 0) {
 355                         puts("Forcing bobcat reset\n");
 356                         set_pin(0, 0x00000004, 3); /* clear PD29 (reset arm) */
 357                         udelay(1000);
 358                         set_pin(1, 0x00000004, 3);
 359                 } else
 360                         set_pin(1, 0x00000004, 3); /* don't reset arm */
 361         }
 362 }
 363 #endif
 364
 365 int ethernet_present(void)
 366 {
 367         struct km_bec_fpga *base =
 368                 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 369
 370         return in_8(&base->bprth) & PIGGY_PRESENT;
 371 }
 372
 373 /*
 374  * Early board initalization.
 375  */
 376 int board_early_init_r(void)
 377 {
 378         struct km_bec_fpga *base =
 379                 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 380
 381         /* setup the UPIOx */
 382         /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
 383         out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
 384         /* SCC4 enable, halfduplex, FCC1 powerdown */
 385         out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
 386                 H_OPORTS_FCC1_PW_DWN));
 387
 388 #ifdef CONFIG_MGCOGE3NE
 389         handle_mgcoge3un_reset();
 390 #endif
 391         return 0;
 392 }
 393
 394 int misc_init_r(void)
 395 {
 396         ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
 397         return 0;
 398 }
 399
 400 int hush_init_var(void)
 401 {
 402         ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
 403         return 0;
 404 }
 405
 406 #define SDA_MASK        0x00010000
 407 #define SCL_MASK        0x00020000
 408
 409 static void set_pin(int state, unsigned long mask, int port)
 410 {
 411         ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port);
 412
 413         if (state)
 414                 setbits_be32(&iop->pdat, mask);
 415         else
 416                 clrbits_be32(&iop->pdat, mask);
 417
 418         setbits_be32(&iop->pdir, mask);
 419 }
 420
 421 static int get_pin(unsigned long mask, int port)
 422 {
 423         ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port);
 424
 425         clrbits_be32(&iop->pdir, mask);
 426         return 0 != (in_be32(&iop->pdat) & mask);
 427 }
 428
 429 void set_sda(int state)
 430 {
 431         set_pin(state, SDA_MASK, 3);
 432 }
 433
 434 void set_scl(int state)
 435 {
 436         set_pin(state, SCL_MASK, 3);
 437 }
 438
 439 int get_sda(void)
 440 {
 441         return get_pin(SDA_MASK, 3);
 442 }
 443
 444 int get_scl(void)
 445 {
 446         return get_pin(SCL_MASK, 3);
 447 }
 448
 449 int ft_board_setup(void *blob, bd_t *bd)
 450 {
 451         ft_cpu_setup(blob, bd);
 452
 453         return 0;
 454 }
 455
 456 #if defined(CONFIG_MGCOGE3NE)
 457 int get_testpin(void)
 458 {
 459         /* Testpin is Port C pin 29 - enable = low */
 460         int testpin = !get_pin(0x00000004, 2);
 461         return testpin;
 462 }
 463 #endif