board/keymile/km83xx/km83xx.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * (C) Copyright 2008 - 2010
  12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #include <common.h>
  18 #include <ioports.h>
  19 #include <mpc83xx.h>
  20 #include <i2c.h>
  21 #include <miiphy.h>
  22 #include <asm/io.h>
  23 #include <asm/mmu.h>
  24 #include <asm/processor.h>
  25 #include <pci.h>
  26 #include <libfdt.h>
  27 #include <post.h>
  28
  29 #include "../common/common.h"
  30
  31 const qe_iop_conf_t qe_iop_conf_tab[] = {
  32         /* port pin dir open_drain assign */
  33 #if defined(CONFIG_MPC8360)
  34         /* MDIO */
  35         {0,  1, 3, 0, 2}, /* MDIO */
  36         {0,  2, 1, 0, 1}, /* MDC */
  37
  38         /* UCC4 - UEC */
  39         {1, 14, 1, 0, 1}, /* TxD0 */
  40         {1, 15, 1, 0, 1}, /* TxD1 */
  41         {1, 20, 2, 0, 1}, /* RxD0 */
  42         {1, 21, 2, 0, 1}, /* RxD1 */
  43         {1, 18, 1, 0, 1}, /* TX_EN */
  44         {1, 26, 2, 0, 1}, /* RX_DV */
  45         {1, 27, 2, 0, 1}, /* RX_ER */
  46         {1, 24, 2, 0, 1}, /* COL */
  47         {1, 25, 2, 0, 1}, /* CRS */
  48         {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
  49         {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
  50
  51         /* DUART - UART2 */
  52         {5,  0, 1, 0, 2}, /* UART2_SOUT */
  53         {5,  2, 1, 0, 1}, /* UART2_RTS */
  54         {5,  3, 2, 0, 2}, /* UART2_SIN */
  55         {5,  1, 2, 0, 3}, /* UART2_CTS */
  56 #elif !defined(CONFIG_MPC8309)
  57         /* Local Bus */
  58         {0, 16, 1, 0, 3}, /* LA00 */
  59         {0, 17, 1, 0, 3}, /* LA01 */
  60         {0, 18, 1, 0, 3}, /* LA02 */
  61         {0, 19, 1, 0, 3}, /* LA03 */
  62         {0, 20, 1, 0, 3}, /* LA04 */
  63         {0, 21, 1, 0, 3}, /* LA05 */
  64         {0, 22, 1, 0, 3}, /* LA06 */
  65         {0, 23, 1, 0, 3}, /* LA07 */
  66         {0, 24, 1, 0, 3}, /* LA08 */
  67         {0, 25, 1, 0, 3}, /* LA09 */
  68         {0, 26, 1, 0, 3}, /* LA10 */
  69         {0, 27, 1, 0, 3}, /* LA11 */
  70         {0, 28, 1, 0, 3}, /* LA12 */
  71         {0, 29, 1, 0, 3}, /* LA13 */
  72         {0, 30, 1, 0, 3}, /* LA14 */
  73         {0, 31, 1, 0, 3}, /* LA15 */
  74
  75         /* MDIO */
  76         {3,  4, 3, 0, 2}, /* MDIO */
  77         {3,  5, 1, 0, 2}, /* MDC */
  78
  79         /* UCC4 - UEC */
  80         {1, 18, 1, 0, 1}, /* TxD0 */
  81         {1, 19, 1, 0, 1}, /* TxD1 */
  82         {1, 22, 2, 0, 1}, /* RxD0 */
  83         {1, 23, 2, 0, 1}, /* RxD1 */
  84         {1, 26, 2, 0, 1}, /* RxER */
  85         {1, 28, 2, 0, 1}, /* Rx_DV */
  86         {1, 30, 1, 0, 1}, /* TxEN */
  87         {1, 31, 2, 0, 1}, /* CRS */
  88         {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
  89 #endif
  90
  91         /* END of table */
  92         {0,  0, 0, 0, QE_IOP_TAB_END},
  93 };
  94
  95 #if defined(CONFIG_SUVD3)
  96 const uint upma_table[] = {
  97         0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
  98         0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
  99         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
 100         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
 101         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
 102         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
 103         0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
 104         0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
 105         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
 106         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
 107         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
 108         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
 109         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
 110         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
 111         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
 112         0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01  /* Words 60 to 63 */
 113 };
 114 #endif
 115
 116 static int piggy_present(void)
 117 {
 118         struct km_bec_fpga __iomem *base =
 119                 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
 120
 121         return in_8(&base->bprth) & PIGGY_PRESENT;
 122 }
 123
 124 #if defined(CONFIG_KMVECT1)
 125 int ethernet_present(void)
 126 {
 127         /* ethernet port connected to simple switch without piggy */
 128         return 1;
 129 }
 130 #else
 131 int ethernet_present(void)
 132 {
 133         return piggy_present();
 134 }
 135 #endif
 136
 137
 138 int board_early_init_r(void)
 139 {
 140         struct km_bec_fpga *base =
 141                 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 142 #if defined(CONFIG_SUVD3)
 143         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 144         fsl_lbc_t *lbc = &immap->im_lbc;
 145         u32 *mxmr = &lbc->mamr;
 146 #endif
 147
 148 #if defined(CONFIG_MPC8360)
 149         unsigned short  svid;
 150         /*
 151          * Because of errata in the UCCs, we have to write to the reserved
 152          * registers to slow the clocks down.
 153          */
 154         svid =  SVR_REV(mfspr(SVR));
 155         switch (svid) {
 156         case 0x0020:
 157                 /*
 158                  * MPC8360ECE.pdf QE_ENET10 table 4:
 159                  * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
 160                  * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
 161                  */
 162                 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
 163                 break;
 164         case 0x0021:
 165                 /*
 166                  * MPC8360ECE.pdf QE_ENET10 table 4:
 167                  * IMMR + 0x14AC[24:27] = 1010
 168                  */
 169                 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
 170                         0x00000050, 0x000000a0);
 171                 break;
 172         }
 173 #endif
 174
 175         /* enable the PHY on the PIGGY */
 176         setbits_8(&base->pgy_eth, 0x01);
 177         /* enable the Unit LED (green) */
 178         setbits_8(&base->oprth, WRL_BOOT);
 179         /* enable Application Buffer */
 180         setbits_8(&base->oprtl, OPRTL_XBUFENA);
 181
 182 #if defined(CONFIG_SUVD3)
 183         /* configure UPMA for APP1 */
 184         upmconfig(UPMA, (uint *) upma_table,
 185                 sizeof(upma_table) / sizeof(uint));
 186         out_be32(mxmr, CONFIG_SYS_MAMR);
 187 #endif
 188         return 0;
 189 }
 190
 191 int misc_init_r(void)
 192 {
 193         return 0;
 194 }
 195
 196 #if defined(CONFIG_KMVECT1)
 197 #include <mv88e6352.h>
 198 /* Marvell MV88E6122 switch configuration */
 199 static struct mv88e_sw_reg extsw_conf[] = {
 200         /* port 1, FRONT_MDI, autoneg */
 201         { PORT(1), PORT_PHY, NO_SPEED_FOR },
 202         { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 203         { PHY(1), PHY_1000_CTRL, NO_ADV },
 204         { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN },
 205         { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
 206                 FULL_DUPLEX },
 207         /* port 2, unused */
 208         { PORT(2), PORT_CTRL, PORT_DIS },
 209         { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
 210         { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
 211         /* port 3, BP_MII (CPU), PHY mode, 100BASE */
 212         { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 213         /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */
 214         { PORT(4), PORT_STATUS, NO_PHY_DETECT },
 215         { PORT(4), PORT_PHY, SPEED_1000_FOR },
 216         { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 217         /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */
 218         { PORT(5), PORT_STATUS, NO_PHY_DETECT },
 219         { PORT(5), PORT_PHY, SPEED_1000_FOR },
 220         { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 221         /*
 222          * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
 223          * acc . MV-S300889-00D.pdf , clause 4.5
 224          */
 225         { PORT(5), 0x1A, 0xADB1 },
 226         /* port 6, unused, this port has no phy */
 227         { PORT(6), PORT_CTRL, PORT_DIS },
 228 };
 229 #endif
 230
 231 int last_stage_init(void)
 232 {
 233 #if defined(CONFIG_KMVECT1)
 234         struct km_bec_fpga __iomem *base =
 235                 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
 236         u8 tmp_reg;
 237
 238         /* Release mv88e6122 from reset */
 239         tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */
 240         out_8(&base->res1[0], tmp_reg);        /* GP28 as output */
 241         tmp_reg = in_8(&base->gprt3) | 0x10;   /* GP28 to high */
 242         out_8(&base->gprt3, tmp_reg);
 243
 244         /* configure MV88E6122 switch */
 245         char *name = "UEC2";
 246
 247         if (miiphy_set_current_dev(name))
 248                 return 0;
 249
 250         mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
 251                 ARRAY_SIZE(extsw_conf));
 252
 253         mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
 254
 255         if (piggy_present()) {
 256                 setenv("ethact", "UEC2");
 257                 setenv("netdev", "eth1");
 258                 puts("using PIGGY for network boot\n");
 259         } else {
 260                 setenv("netdev", "eth0");
 261                 puts("using frontport for network boot\n");
 262         }
 263 #endif
 264
 265 #if defined(CONFIG_KMCOGE5NE)
 266         struct bfticu_iomap *base =
 267                 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
 268         u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
 269
 270         if (dip_switch != 0) {
 271                 /* start bootloader */
 272                 puts("DIP:   Enabled\n");
 273                 setenv("actual_bank", "0");
 274         }
 275 #endif
 276         set_km_env();
 277         return 0;
 278 }
 279
 280 int fixed_sdram(void)
 281 {
 282         immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 283         u32 msize = 0;
 284         u32 ddr_size;
 285         u32 ddr_size_log2;
 286
 287         out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
 288         out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
 289         out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
 290         out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
 291         out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
 292         out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
 293         out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
 294         out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
 295         out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
 296         out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
 297         out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
 298         out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
 299         out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
 300         udelay(200);
 301         setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
 302
 303         msize = CONFIG_SYS_DDR_SIZE << 20;
 304         disable_addr_trans();
 305         msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
 306         enable_addr_trans();
 307         msize /= (1024 * 1024);
 308         if (CONFIG_SYS_DDR_SIZE != msize) {
 309                 for (ddr_size = msize << 20, ddr_size_log2 = 0;
 310                         (ddr_size > 1);
 311                         ddr_size = ddr_size >> 1, ddr_size_log2++)
 312                         if (ddr_size & 1)
 313                                 return -1;
 314                 out_be32(&im->sysconf.ddrlaw[0].ar,
 315                         (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
 316                 out_be32(&im->ddr.csbnds[0].csbnds,
 317                         (((msize / 16) - 1) & 0xff));
 318         }
 319
 320         return msize;
 321 }
 322
 323 phys_size_t initdram(int board_type)
 324 {
 325         immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 326         u32 msize = 0;
 327
 328         if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
 329                 return -1;
 330
 331         out_be32(&im->sysconf.ddrlaw[0].bar,
 332                 CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
 333         msize = fixed_sdram();
 334
 335 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 336         /*
 337          * Initialize DDR ECC byte
 338          */
 339         ddr_enable_ecc(msize * 1024 * 1024);
 340 #endif
 341
 342         /* return total bus SDRAM size(bytes)  -- DDR */
 343         return msize * 1024 * 1024;
 344 }
 345
 346 int checkboard(void)
 347 {
 348         puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
 349
 350         if (piggy_present())
 351                 puts(" with PIGGY.");
 352         puts("\n");
 353         return 0;
 354 }
 355
 356 #if defined(CONFIG_OF_BOARD_SETUP)
 357 void ft_board_setup(void *blob, bd_t *bd)
 358 {
 359         ft_cpu_setup(blob, bd);
 360 }
 361 #endif
 362
 363 #if defined(CONFIG_HUSH_INIT_VAR)
 364 int hush_init_var(void)
 365 {
 366         ivm_read_eeprom();
 367         return 0;
 368 }
 369 #endif
 370
 371 #if defined(CONFIG_POST)
 372 int post_hotkeys_pressed(void)
 373 {
 374         int testpin = 0;
 375         struct km_bec_fpga *base =
 376                 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 377         int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
 378         testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
 379         debug("post_hotkeys_pressed: %d\n", !testpin);
 380         return testpin;
 381 }
 382
 383 ulong post_word_load(void)
 384 {
 385         void* addr = (ulong *) (CPM_POST_WORD_ADDR);
 386         debug("post_word_load 0x%08lX:  0x%08X\n", (ulong)addr, in_le32(addr));
 387         return in_le32(addr);
 388
 389 }
 390 void post_word_store(ulong value)
 391 {
 392         void* addr = (ulong *) (CPM_POST_WORD_ADDR);
 393         debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
 394         out_le32(addr, value);
 395 }
 396
 397 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 398 {
 399         *vstart = CONFIG_SYS_MEMTEST_START;
 400         *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
 401         debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
 402
 403         return 0;
 404 }
 405 #endif