board/logicpd/omap3som/omap3logic.c

   1 /*
   2  * (C) Copyright 2011
   3  * Logic Product Development <www.logicpd.com>
   4  *
   5  * Author :
   6  *      Peter Barada <peter.barada@logicpd.com>
   7  *
   8  * Derived from Beagle Board and 3430 SDP code by
   9  *      Richard Woodruff <r-woodruff2@ti.com>
  10  *      Syed Mohammed Khasim <khasim@ti.com>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <ns16550.h>
  17 #include <netdev.h>
  18 #include <flash.h>
  19 #include <nand.h>
  20 #include <i2c.h>
  21 #include <twl4030.h>
  22 #include <asm/io.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/mux.h>
  25 #include <asm/arch/mem.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/gpio.h>
  28 #include <asm/mach-types.h>
  29 #include <linux/mtd/rawnand.h>
  30 #include <asm/omap_musb.h>
  31 #include <linux/errno.h>
  32 #include <linux/usb/ch9.h>
  33 #include <linux/usb/gadget.h>
  34 #include <linux/usb/musb.h>
  35 #include "omap3logic.h"
  36 #ifdef CONFIG_USB_EHCI_HCD
  37 #include <usb.h>
  38 #include <asm/ehci-omap.h>
  39 #endif
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 /* This is only needed until SPL gets OF support */
  44 #ifdef CONFIG_SPL_BUILD
  45 static const struct ns16550_platdata omap3logic_serial = {
  46         .base = OMAP34XX_UART1,
  47         .reg_shift = 2,
  48         .clock = V_NS16550_CLK,
  49         .fcr = UART_FCR_DEFVAL,
  50 };
  51
  52 U_BOOT_DEVICE(omap3logic_uart) = {
  53         "ns16550_serial",
  54         &omap3logic_serial
  55 };
  56 #endif
  57
  58 /*
  59  * two dimensional array of strucures containining board name and Linux
  60  * machine IDs; row it selected based on CPU column is slected based
  61  * on hsusb0_data5 pin having a pulldown resistor
  62  */
  63 static struct board_id {
  64         char *name;
  65         int machine_id;
  66         char *fdtfile;
  67 } boards[2][2] = {
  68         {
  69                 {
  70                         .name           = "OMAP35xx SOM LV",
  71                         .machine_id     = MACH_TYPE_OMAP3530_LV_SOM,
  72                         .fdtfile        = "logicpd-som-lv-35xx-devkit.dtb",
  73                 },
  74                 {
  75                         .name           = "OMAP35xx Torpedo",
  76                         .machine_id     = MACH_TYPE_OMAP3_TORPEDO,
  77                         .fdtfile        = "logicpd-torpedo-35xx-devkit.dtb",
  78                 },
  79         },
  80         {
  81                 {
  82                         .name           = "DM37xx SOM LV",
  83                         .fdtfile        = "logicpd-som-lv-37xx-devkit.dtb",
  84                 },
  85                 {
  86                         .name           = "DM37xx Torpedo",
  87                         .fdtfile        = "logicpd-torpedo-37xx-devkit.dtb",
  88                 },
  89         },
  90 };
  91
  92 #ifdef CONFIG_SPL_OS_BOOT
  93 int spl_start_uboot(void)
  94 {
  95         /* break into full u-boot on 'c' */
  96         return serial_tstc() && serial_getc() == 'c';
  97 }
  98 #endif
  99
 100 #if defined(CONFIG_SPL_BUILD)
 101 /*
 102  * Routine: get_board_mem_timings
 103  * Description: If we use SPL then there is no x-loader nor config header
 104  * so we have to setup the DDR timings ourself on the first bank.  This
 105  * provides the timing values back to the function that configures
 106  * the memory.
 107  */
 108 void get_board_mem_timings(struct board_sdrc_timings *timings)
 109 {
 110         timings->mr = MICRON_V_MR_165;
 111         /* 256MB DDR */
 112         timings->mcfg = MICRON_V_MCFG_200(256 << 20);
 113         timings->ctrla = MICRON_V_ACTIMA_200;
 114         timings->ctrlb = MICRON_V_ACTIMB_200;
 115         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 116 }
 117
 118 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
 119 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
 120 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
 121
 122 void spl_board_prepare_for_linux(void)
 123 {
 124         /* The Micron NAND starts locked which
 125          * prohibits mounting the NAND as RW
 126          * The following commands are what unlocks
 127          * the NAND to become RW Falcon Mode does not
 128          * have as many smarts as U-Boot, but Logic PD
 129          * only makes NAND with 512MB so these hard coded
 130          * values should work for all current models
 131          */
 132
 133         writeb(0x70, GPMC_NAND_COMMAND_0);
 134         writeb(-1, GPMC_NAND_DATA_0);
 135         writeb(0x7a, GPMC_NAND_COMMAND_0);
 136         writeb(0x00, GPMC_NAND_ADDRESS_0);
 137         writeb(0x00, GPMC_NAND_ADDRESS_0);
 138         writeb(0x00, GPMC_NAND_ADDRESS_0);
 139         writeb(-1, GPMC_NAND_COMMAND_0);
 140
 141         /* Begin address 0 */
 142         writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
 143         writeb(0x00, GPMC_NAND_ADDRESS_0);
 144         writeb(0x00, GPMC_NAND_ADDRESS_0);
 145         writeb(0x00, GPMC_NAND_ADDRESS_0);
 146         writeb(-1, GPMC_NAND_DATA_0);
 147
 148         /* Ending address at the end of Flash */
 149         writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
 150         writeb(0xc0, GPMC_NAND_ADDRESS_0);
 151         writeb(0xff, GPMC_NAND_ADDRESS_0);
 152         writeb(0x03, GPMC_NAND_ADDRESS_0);
 153         writeb(-1, GPMC_NAND_DATA_0);
 154         writeb(0x79, GPMC_NAND_COMMAND_0);
 155         writeb(-1, GPMC_NAND_DATA_0);
 156         writeb(-1, GPMC_NAND_DATA_0);
 157 }
 158 #endif
 159
 160 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
 161 static struct musb_hdrc_config musb_config = {
 162         .multipoint     = 1,
 163         .dyn_fifo       = 1,
 164         .num_eps        = 16,
 165         .ram_bits       = 12,
 166 };
 167
 168 static struct omap_musb_board_data musb_board_data = {
 169         .interface_type = MUSB_INTERFACE_ULPI,
 170 };
 171
 172 static struct musb_hdrc_platform_data musb_plat = {
 173 #if defined(CONFIG_USB_MUSB_HOST)
 174         .mode           = MUSB_HOST,
 175 #elif defined(CONFIG_USB_MUSB_GADGET)
 176         .mode           = MUSB_PERIPHERAL,
 177 #else
 178 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
 179 #endif
 180         .config         = &musb_config,
 181         .power          = 100,
 182         .platform_ops   = &omap2430_ops,
 183         .board_data     = &musb_board_data,
 184 };
 185 #endif
 186
 187 #if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
 188 /* Call usb_stop() before starting the kernel */
 189 void show_boot_progress(int val)
 190 {
 191         if (val == BOOTSTAGE_ID_RUN_OS)
 192                 usb_stop();
 193 }
 194
 195 static struct omap_usbhs_board_data usbhs_bdata = {
 196         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 197         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
 198         .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
 199 };
 200
 201 int ehci_hcd_init(int index, enum usb_init_type init,
 202                 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 203 {
 204         return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 205 }
 206
 207 int ehci_hcd_stop(int index)
 208 {
 209         return omap_ehci_hcd_stop();
 210 }
 211
 212 #endif /* CONFIG_USB_EHCI_HCD */
 213
 214
 215 /*
 216  * Routine: misc_init_r
 217  * Description: Configure board specific parts
 218  */
 219 int misc_init_r(void)
 220 {
 221         twl4030_power_init();
 222         omap_die_id_display();
 223
 224 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
 225         musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
 226 #endif
 227
 228         return 0;
 229 }
 230
 231 /*
 232  * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
 233  */
 234 #define BOARD_ID_GPIO   189 /* hsusb0_data5 pin */
 235
 236 /*
 237  * Routine: board_init
 238  * Description: Early hardware init.
 239  */
 240 int board_init(void)
 241 {
 242         gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
 243
 244         /* boot param addr */
 245         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 246
 247         return 0;
 248 }
 249
 250 #ifdef CONFIG_BOARD_LATE_INIT
 251
 252 static void unlock_nand(void)
 253 {
 254         int dev = nand_curr_device;
 255         struct mtd_info *mtd;
 256
 257         mtd = get_nand_dev_by_index(dev);
 258         nand_unlock(mtd, 0, mtd->size, 0);
 259 }
 260
 261 int board_late_init(void)
 262 {
 263         struct board_id *board;
 264         unsigned int val;
 265
 266         /*
 267          * To identify between a SOM LV and Torpedo module,
 268          * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
 269          * Drive the pin (and let it soak), then read it back.
 270          * If the pin is still high its a Torpedo.  If low its a SOM LV
 271          */
 272
 273         /* Mux hsusb0_data5 as a GPIO */
 274         MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M4));
 275
 276         if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
 277
 278                 /*
 279                  * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
 280                  * will drain the voltage.
 281                  */
 282                 gpio_direction_output(BOARD_ID_GPIO, 0);
 283                 gpio_set_value(BOARD_ID_GPIO, 1);
 284
 285                 /* Let it soak for a bit */
 286                 sdelay(0x100);
 287
 288                 /*
 289                  * Read state of BOARD_ID_GPIO as an input and if its set.
 290                  * If so the board is a Torpedo
 291                  */
 292                 gpio_direction_input(BOARD_ID_GPIO);
 293                 val = gpio_get_value(BOARD_ID_GPIO);
 294                 gpio_free(BOARD_ID_GPIO);
 295
 296                 board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
 297                 printf("Board: %s\n", board->name);
 298
 299                 /* Set the machine_id passed to Linux */
 300                 if (board->machine_id)
 301                         gd->bd->bi_arch_number = board->machine_id;
 302
 303                 /* If the user has not set fdtimage, set the default */
 304                 if (!env_get("fdtimage"))
 305                         env_set("fdtimage", board->fdtfile);
 306         }
 307
 308         /* restore hsusb0_data5 pin as hsusb0_data5 */
 309         MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0));
 310
 311 #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
 312         unlock_nand();
 313 #endif
 314         return 0;
 315 }
 316 #endif
 317
 318 #if defined(CONFIG_MMC)
 319 int board_mmc_init(bd_t *bis)
 320 {
 321         return omap_mmc_init(0, 0, 0, -1, -1);
 322 }
 323 #endif
 324
 325 #if defined(CONFIG_MMC)
 326 void board_mmc_power_init(void)
 327 {
 328         twl4030_power_mmc_init(0);
 329 }
 330 #endif
 331
 332 #ifdef CONFIG_SMC911X
 333 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
 334 static const u32 gpmc_lan92xx_config[] = {
 335         NET_LAN92XX_GPMC_CONFIG1,
 336         NET_LAN92XX_GPMC_CONFIG2,
 337         NET_LAN92XX_GPMC_CONFIG3,
 338         NET_LAN92XX_GPMC_CONFIG4,
 339         NET_LAN92XX_GPMC_CONFIG5,
 340         NET_LAN92XX_GPMC_CONFIG6,
 341 };
 342
 343 int board_eth_init(bd_t *bis)
 344 {
 345         enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
 346                         CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
 347
 348         return smc911x_initialize(0, CONFIG_SMC911X_BASE);
 349 }
 350 #endif
 351
 352