2 * (C) Copyright 2007-2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/ppc440.h>
24 #include <asm/processor.h>
25 #include <asm/ppc4xx-gpio.h>
29 #include <mtd/cfi_flash.h>
31 DECLARE_GLOBAL_DATA_PTR
;
33 static phys_addr_t lwmon5_cfi_flash_bank_addr
[2] = CONFIG_SYS_FLASH_BANKS_LIST
;
35 ulong
flash_get_size(ulong base
, int banknum
);
36 int misc_init_r_kbd(void);
38 int board_early_init_f(void)
40 u32 sdr0_pfc1
, sdr0_pfc2
;
43 /* PLB Write pipelining disabled. Denali Core workaround */
44 mtdcr(PLB4A0_ACR
, 0xDE000000);
45 mtdcr(PLB4A1_ACR
, 0xDE000000);
47 /*--------------------------------------------------------------------
48 * Setup the interrupt controller polarities, triggers, etc.
49 *-------------------------------------------------------------------*/
50 mtdcr(UIC0SR
, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
51 mtdcr(UIC0ER
, 0x00000000); /* disable all */
52 mtdcr(UIC0CR
, 0x00000000); /* we have not critical interrupts at the moment */
53 mtdcr(UIC0PR
, 0xFFBFF1EF); /* Adjustment of the polarity */
54 mtdcr(UIC0TR
, 0x00000900); /* per ref-board manual */
55 mtdcr(UIC0VR
, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
56 mtdcr(UIC0SR
, 0xffffffff); /* clear all */
58 mtdcr(UIC1SR
, 0xffffffff); /* clear all */
59 mtdcr(UIC1ER
, 0x00000000); /* disable all */
60 mtdcr(UIC1CR
, 0x00000000); /* all non-critical */
61 mtdcr(UIC1PR
, 0xFFFFC6A5); /* Adjustment of the polarity */
62 mtdcr(UIC1TR
, 0x60000040); /* per ref-board manual */
63 mtdcr(UIC1VR
, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
64 mtdcr(UIC1SR
, 0xffffffff); /* clear all */
66 mtdcr(UIC2SR
, 0xffffffff); /* clear all */
67 mtdcr(UIC2ER
, 0x00000000); /* disable all */
68 mtdcr(UIC2CR
, 0x00000000); /* all non-critical */
69 mtdcr(UIC2PR
, 0x27C00000); /* Adjustment of the polarity */
70 mtdcr(UIC2TR
, 0x3C000000); /* per ref-board manual */
71 mtdcr(UIC2VR
, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
72 mtdcr(UIC2SR
, 0xffffffff); /* clear all */
74 /* Trace Pins are disabled. SDR0_PFC0 Register */
75 mtsdr(SDR0_PFC0
, 0x0);
77 /* select Ethernet pins */
78 mfsdr(SDR0_PFC1
, sdr0_pfc1
);
80 sdr0_pfc1
= (sdr0_pfc1
& ~SDR0_PFC1_SELECT_MASK
) |
81 SDR0_PFC1_SELECT_CONFIG_6
;
82 mfsdr(SDR0_PFC2
, sdr0_pfc2
);
83 sdr0_pfc2
= (sdr0_pfc2
& ~SDR0_PFC2_SELECT_MASK
) |
84 SDR0_PFC2_SELECT_CONFIG_6
;
86 /* enable SPI (SCP) */
87 sdr0_pfc1
= (sdr0_pfc1
& ~SDR0_PFC1_SIS_MASK
) | SDR0_PFC1_SIS_SCP_SEL
;
89 mtsdr(SDR0_PFC2
, sdr0_pfc2
);
90 mtsdr(SDR0_PFC1
, sdr0_pfc1
);
92 mtsdr(SDR0_PFC4
, 0x80000000);
94 /* PCI arbiter disabled */
95 /* PCI Host Configuration disbaled */
96 mfsdr(SDR0_PCI0
, reg
);
98 mtsdr(SDR0_PCI0
, 0x00000000 | reg
);
100 gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP
, 1);
102 #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
103 /* enable the LSB transmitter */
104 gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE
, 1);
105 /* enable the CAN transmitter */
106 gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE
, 1);
108 reg
= 0; /* reuse as counter */
109 out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR
,
110 in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR
)
111 & ~CONFIG_SYS_DSPIC_TEST_MASK
);
112 while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY
) && reg
++ < 1000) {
115 if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY
)) {
116 /* set "boot error" flag */
117 out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR
,
118 in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR
) |
119 CONFIG_SYS_DSPIC_TEST_MASK
);
125 * The PHY's need a 2nd reset pulse, since the MDIO address is latched
126 * upon reset, and with the first reset upon powerup, the addresses are
127 * not latched reliable, since the IRQ line is multiplexed with an
128 * MDIO address. A 2nd reset at this time will make sure, that the
129 * correct address is latched.
131 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST
, 1);
132 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST
, 1);
134 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST
, 0);
135 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST
, 0);
137 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST
, 1);
138 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST
, 1);
144 * Override weak default with board specific version
146 phys_addr_t
cfi_flash_bank_addr(int bank
)
148 return lwmon5_cfi_flash_bank_addr
[bank
];
152 * Override the weak default mapping function with a board specific one
154 u32
flash_get_bank_size(int cs
, int idx
)
156 return flash_info
[idx
].size
;
159 int board_early_init_r(void)
164 * lwmon5 is manufactured in 2 different board versions:
165 * The lwmon5a board has 64MiB NOR flash instead of the
166 * 128MiB of the original lwmon5. Unfortunately the CFI driver
167 * will report 2 banks of 64MiB even for the smaller flash
168 * chip, since the bank is mirrored. To fix this, we bring
169 * one bank into CFI query mode and read its response. This
170 * enables us to detect the real number of flash devices/
171 * banks which will be used later on by the common CFI driver.
174 /* Put bank 0 into CFI command mode and read */
175 out_be32((void *)CONFIG_SYS_FLASH0
, 0x00980098);
176 val0
= in_be32((void *)CONFIG_SYS_FLASH0
+ FLASH_OFFSET_CFI_RESP
);
177 val1
= in_be32((void *)CONFIG_SYS_FLASH1
+ FLASH_OFFSET_CFI_RESP
);
179 /* Reset flash again out of query mode */
180 out_be32((void *)CONFIG_SYS_FLASH0
, 0x00f000f0);
182 /* When not identical, we have 2 different flash devices/banks */
187 * Now we're sure that we're running on a LWMON5a board with
188 * only 64MiB NOR flash in one bank:
190 * Set flash base address and bank count for CFI driver probing.
192 cfi_flash_num_flash_banks
= 1;
193 lwmon5_cfi_flash_bank_addr
[0] = CONFIG_SYS_FLASH0
;
198 int misc_init_r(void)
203 unsigned long usb2d0cr
= 0;
204 unsigned long usb2phy0cr
, usb2h0cr
= 0;
205 unsigned long sdr0_pfc1
, sdr0_srst
;
211 /* Re-do sizing to get full correct info */
213 /* adjust flash start and offset */
214 gd
->bd
->bi_flashstart
= 0 - gd
->bd
->bi_flashsize
;
215 gd
->bd
->bi_flashoffset
= 0;
218 size_val
= ffs(gd
->bd
->bi_flashsize
) - 21;
219 pbcr
= (pbcr
& 0x0001ffff) | gd
->bd
->bi_flashstart
| (size_val
<< 17);
223 * Re-check to get correct base address
225 flash_get_size(gd
->bd
->bi_flashstart
, 0);
227 /* Monitor protection ON by default */
228 flash_protect(FLAG_PROTECT_SET
, -CONFIG_SYS_MONITOR_LEN
, 0xffffffff,
229 &flash_info
[cfi_flash_num_flash_banks
- 1]);
231 /* Env protection ON by default */
232 flash_protect(FLAG_PROTECT_SET
, CONFIG_ENV_ADDR_REDUND
,
233 CONFIG_ENV_ADDR_REDUND
+ 2 * CONFIG_ENV_SECT_SIZE
- 1,
234 &flash_info
[cfi_flash_num_flash_banks
- 1]);
241 /* Reset of USB2PHY0 must be active at least 10 us */
242 mtsdr(SDR0_SRST0
, SDR0_SRST0_USB2H
| SDR0_SRST0_USB2D
);
245 mtsdr(SDR0_SRST1
, SDR0_SRST1_USB20PHY
| SDR0_SRST1_USB2HUTMI
|
246 SDR0_SRST1_USB2HPHY
| SDR0_SRST1_OPBA2
|
247 SDR0_SRST1_PLB42OPB1
| SDR0_SRST1_OPB2PLB40
);
252 /* 1. Set internal PHY configuration */
254 mfsdr(SDR0_PFC1
, sdr0_pfc1
);
255 mfsdr(SDR0_USB0
, usb2d0cr
);
256 mfsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
257 mfsdr(SDR0_USB2H0CR
, usb2h0cr
);
259 usb2phy0cr
= usb2phy0cr
& ~SDR0_USB2PHY0CR_XOCLK_MASK
;
260 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_XOCLK_EXTERNAL
; /*0*/
261 usb2phy0cr
= usb2phy0cr
& ~SDR0_USB2PHY0CR_WDINT_MASK
;
262 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ
; /*1*/
263 usb2phy0cr
= usb2phy0cr
& ~SDR0_USB2PHY0CR_DVBUS_MASK
;
264 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DVBUS_PUREN
; /*1*/
265 usb2phy0cr
= usb2phy0cr
& ~SDR0_USB2PHY0CR_DWNSTR_MASK
;
266 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_DWNSTR_HOST
; /*1*/
267 usb2phy0cr
= usb2phy0cr
& ~SDR0_USB2PHY0CR_UTMICN_MASK
;
268 usb2phy0cr
= usb2phy0cr
| SDR0_USB2PHY0CR_UTMICN_HOST
; /*1*/
271 * An 8-bit/60MHz interface is the only possible alternative
272 * when connecting the Device to the PHY
274 usb2h0cr
= usb2h0cr
& ~SDR0_USB2H0CR_WDINT_MASK
;
275 usb2h0cr
= usb2h0cr
| SDR0_USB2H0CR_WDINT_16BIT_30MHZ
; /*1*/
277 mtsdr(SDR0_PFC1
, sdr0_pfc1
);
278 mtsdr(SDR0_USB0
, usb2d0cr
);
279 mtsdr(SDR0_USB2PHY0CR
, usb2phy0cr
);
280 mtsdr(SDR0_USB2H0CR
, usb2h0cr
);
282 /* 2. De-assert internal PHY reset */
283 mfsdr(SDR0_SRST1
, sdr0_srst
);
284 sdr0_srst
= sdr0_srst
& ~SDR0_SRST1_USB20PHY
;
285 mtsdr(SDR0_SRST1
, sdr0_srst
);
287 /* 3. Wait for more than 1 ms */
290 /* 4. De-assert USB 2.0 Host main reset */
291 mfsdr(SDR0_SRST0
, sdr0_srst
);
292 sdr0_srst
= sdr0_srst
&~ SDR0_SRST0_USB2H
;
293 mtsdr(SDR0_SRST0
, sdr0_srst
);
296 /* 5. De-assert reset of OPB2 cores */
297 mfsdr(SDR0_SRST1
, sdr0_srst
);
298 sdr0_srst
= sdr0_srst
&~ SDR0_SRST1_PLB42OPB1
;
299 sdr0_srst
= sdr0_srst
&~ SDR0_SRST1_OPB2PLB40
;
300 sdr0_srst
= sdr0_srst
&~ SDR0_SRST1_OPBA2
;
301 mtsdr(SDR0_SRST1
, sdr0_srst
);
304 /* 6. Set EHCI Configure FLAG */
306 /* 7. Reassert internal PHY reset: */
307 mtsdr(SDR0_SRST1
, SDR0_SRST1_USB20PHY
);
313 mtsdr(SDR0_SRST1
, 0x00000000);
314 mtsdr(SDR0_SRST0
, 0x00000000);
316 printf("USB: Host(int phy) Device(ext phy)\n");
319 * Clear PLB4A0_ACR[WRP]
320 * This fix will make the MAL burst disabling patch for the Linux
321 * EMAC driver obsolete.
323 reg
= mfdcr(PLB4A0_ACR
) & ~PLB4Ax_ACR_WRP_MASK
;
324 mtdcr(PLB4A0_ACR
, reg
);
327 * Init matrix keyboard
336 char *s
= getenv("serial#");
338 puts("Board: lwmon5");
349 void hw_watchdog_reset(void)
352 #if defined(CONFIG_WD_MAX_RATE)
353 unsigned long long ct
= get_ticks();
356 * Don't allow watch-dog triggering more frequently than
357 * the predefined value CONFIG_WD_MAX_RATE [ticks].
359 if (ct
>= gd
->wdt_last
) {
360 if ((ct
- gd
->wdt_last
) < CONFIG_WD_MAX_RATE
)
363 /* Time base counter had been reset */
364 if (((unsigned long long)(-1) - gd
->wdt_last
+ ct
) <
368 gd
->wdt_last
= get_ticks();
372 * Toggle watchdog output
374 val
= gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG
) == 0 ? 1 : 0;
375 gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG
, val
);
378 int do_eeprom_wp(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
381 return cmd_usage(cmdtp
);
383 if ((strcmp(argv
[1], "on") == 0))
384 gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP
, 1);
385 else if ((strcmp(argv
[1], "off") == 0))
386 gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP
, 0);
388 return cmd_usage(cmdtp
);
394 eepromwp
, 2, 0, do_eeprom_wp
,
395 "eeprom write protect off/on",
396 "<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
399 #if defined(CONFIG_VIDEO)
400 #include <video_fb.h>
403 extern GraphicDevice mb862xx
;
405 static const gdc_regs init_regs
[] = {
406 { 0x0100, 0x00000f00 },
407 { 0x0020, 0x801401df },
408 { 0x0024, 0x00000000 },
409 { 0x0028, 0x00000000 },
410 { 0x002c, 0x00000000 },
411 { 0x0110, 0x00000000 },
412 { 0x0114, 0x00000000 },
413 { 0x0118, 0x01df0280 },
414 { 0x0004, 0x031f0000 },
415 { 0x0008, 0x027f027f },
416 { 0x000c, 0x015f028f },
417 { 0x0010, 0x020c0000 },
418 { 0x0014, 0x01df01ea },
419 { 0x0018, 0x00000000 },
420 { 0x001c, 0x01e00280 },
421 { 0x0100, 0x80010f00 },
425 const gdc_regs
*board_get_regs(void)
430 /* Returns Lime base address */
431 unsigned int board_video_init(void)
434 * Reset Lime controller
436 gpio_write_bit(CONFIG_SYS_GPIO_LIME_S
, 1);
438 gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST
, 1);
440 mb862xx
.winSizeX
= 640;
441 mb862xx
.winSizeY
= 480;
442 mb862xx
.gdfBytesPP
= 2;
443 mb862xx
.gdfIndex
= GDF_15BIT_555RGB
;
445 return CONFIG_SYS_LIME_BASE_0
;
448 #define DEFAULT_BRIGHTNESS 0x64
450 static void board_backlight_brightness(int brightness
)
452 if (brightness
> 0) {
453 /* pwm duty, lamp on */
454 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0
+ 0x00000024), brightness
);
455 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0
+ 0x00000020), 0x701);
458 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0
+ 0x00000024), 0x00);
459 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0
+ 0x00000020), 0x00);
463 void board_backlight_switch(int flag
)
469 param
= getenv("brightness");
470 rc
= param
? simple_strtol(param
, NULL
, 10) : -1;
472 rc
= DEFAULT_BRIGHTNESS
;
476 board_backlight_brightness(rc
);
479 #if defined(CONFIG_CONSOLE_EXTRA_INFO)
481 * Return text to be printed besides the logo.
483 void video_get_info_str(int line_number
, char *info
)
485 if (line_number
== 1)
486 strcpy(info
, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
490 #endif /* CONFIG_CONSOLE_EXTRA_INFO */
491 #endif /* CONFIG_VIDEO */
493 void board_reset(void)
495 gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET
, 1);