2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
5 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/mpc8349_pci.h>
33 #if defined(CONFIG_OF_LIBFDT)
41 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
46 msize
= CONFIG_SYS_DDR_SIZE
;
47 for (ddr_size
= msize
<< 20, ddr_size_log2
= 0;
49 ddr_size
= ddr_size
>> 1, ddr_size_log2
++) {
53 im
->sysconf
.ddrlaw
[0].bar
= CONFIG_SYS_DDR_SDRAM_BASE
& 0xfffff000;
54 im
->sysconf
.ddrlaw
[0].ar
= LAWAR_EN
| ((ddr_size_log2
- 1) &
57 im
->ddr
.csbnds
[0].csbnds
= CONFIG_SYS_DDR_CS0_BNDS
;
58 im
->ddr
.cs_config
[0] = CONFIG_SYS_DDR_CS0_CONFIG
;
59 im
->ddr
.timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
;
60 im
->ddr
.timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
61 im
->ddr
.timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
62 im
->ddr
.timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
;
63 im
->ddr
.sdram_cfg
= CONFIG_SYS_DDR_SDRAM_CFG
;
64 im
->ddr
.sdram_cfg2
= CONFIG_SYS_DDR_SDRAM_CFG2
;
65 im
->ddr
.sdram_mode
= CONFIG_SYS_DDR_MODE
;
66 im
->ddr
.sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
67 im
->ddr
.sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CNTL
;
71 im
->ddr
.sdram_cfg
|= SDRAM_CFG_MEM_EN
;
73 return CONFIG_SYS_DDR_SIZE
;
76 phys_size_t
initdram(int board_type
)
78 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
81 if ((im
->sysconf
.immrbar
& IMMRBAR_BASE_ADDR
) != (u32
) im
)
84 im
->sysconf
.ddrlaw
[0].bar
= CONFIG_SYS_DDR_BASE
& LAWBAR_BAR
;
85 msize
= fixed_sdram();
87 /* return total bus RAM size(bytes) */
88 return msize
* 1024 * 1024;
93 puts("Board: Matrix Vision mvBlueLYNX-M7\n");
98 u8
*dhcp_vendorex_prep(u8
*e
)
102 /* DHCP vendor-class-identifier = 60 */
103 ptr
= getenv("dhcp_vendor-class-identifier");
110 /* DHCP_CLIENT_IDENTIFIER = 61 */
111 ptr
= getenv("dhcp_client_id");
122 u8
*dhcp_vendorex_proc(u8
*popt
)
127 #ifdef CONFIG_HARD_SPI
128 int spi_cs_is_valid(unsigned int bus
, unsigned int cs
)
130 return bus
== 0 && cs
== 0;
133 void spi_cs_activate(struct spi_slave
*slave
)
135 volatile gpio83xx_t
*iopd
= &((immap_t
*)CONFIG_SYS_IMMR
)->gpio
[0];
137 iopd
->dat
&= ~MVBLM7_MMC_CS
;
140 void spi_cs_deactivate(struct spi_slave
*slave
)
142 volatile gpio83xx_t
*iopd
= &((immap_t
*)CONFIG_SYS_IMMR
)->gpio
[0];
144 iopd
->dat
|= ~MVBLM7_MMC_CS
;
148 #if defined(CONFIG_OF_BOARD_SETUP)
149 void ft_board_setup(void *blob
, bd_t
*bd
)
151 ft_cpu_setup(blob
, bd
);
153 ft_pci_setup(blob
, bd
);