board/matrix_vision/mvblm7/pci.c

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
   3  *
   4  * (C) Copyright 2008
   5  * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #if defined(CONFIG_OF_LIBFDT)
  28 #include <libfdt.h>
  29 #endif
  30 #include <pci.h>
  31 #include <mpc83xx.h>
  32 #include <fpga.h>
  33 #include "mvblm7.h"
  34 #include "fpga.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 int mvblm7_load_fpga(void)
  39 {
  40         size_t data_size = 0;
  41         void *fpga_data = NULL;
  42         char *datastr = getenv("fpgadata");
  43         char *sizestr = getenv("fpgadatasize");
  44
  45         if (datastr)
  46                 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
  47         if (sizestr)
  48                 data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
  49
  50         return fpga_load(0, fpga_data, data_size);
  51 }
  52
  53 static struct pci_region pci_regions[] = {
  54         {
  55                 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  56                 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  57                 size: CONFIG_SYS_PCI1_MEM_SIZE,
  58                 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  59         },
  60         {
  61                 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  62                 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  63                 size: CONFIG_SYS_PCI1_MMIO_SIZE,
  64                 flags: PCI_REGION_MEM
  65         },
  66         {
  67                 bus_start: CONFIG_SYS_PCI1_IO_BASE,
  68                 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  69                 size: CONFIG_SYS_PCI1_IO_SIZE,
  70                 flags: PCI_REGION_IO
  71         }
  72 };
  73
  74 void pci_init_board(void)
  75 {
  76         char *s;
  77         int i;
  78         int warmboot;
  79         int load_fpga;
  80         volatile immap_t *immr;
  81         volatile pcictrl83xx_t *pci_ctrl;
  82         volatile gpio83xx_t *gpio;
  83         volatile clk83xx_t *clk;
  84         volatile law83xx_t *pci_law;
  85         struct pci_region *reg[] = { pci_regions };
  86
  87         load_fpga = 1;
  88         immr = (immap_t *) CONFIG_SYS_IMMR;
  89         clk = (clk83xx_t *) &immr->clk;
  90         pci_ctrl = immr->pci_ctrl;
  91         pci_law = immr->sysconf.pcilaw;
  92         gpio  = (volatile gpio83xx_t *)&immr->gpio[0];
  93
  94         s = getenv("skip_fpga");
  95         if (s) {
  96                 printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
  97                 load_fpga = 0;
  98         }
  99
 100         gpio->dat = MV_GPIO_DAT;
 101         gpio->odr = MV_GPIO_ODE;
 102         if (load_fpga)
 103                 gpio->dir = MV_GPIO_OUT;
 104         else
 105                 gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
 106
 107         printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
 108                 immr->sysconf.sicrl);
 109
 110         mvblm7_init_fpga();
 111         if (load_fpga)
 112                 mvblm7_load_fpga();
 113
 114         /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
 115         clk->occr = 0xc0000000;
 116
 117         pci_ctrl[0].gcr = 0;
 118         udelay(2000);
 119         pci_ctrl[0].gcr = 1;
 120
 121         for (i = 0; i < 1000; ++i)
 122                 udelay(1000);
 123
 124         pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 125         pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
 126
 127         pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 128         pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 129
 130         warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
 131
 132         mpc83xx_pci_init(1, reg, warmboot);
 133 }