]>
git.ipfire.org Git - people/ms/u-boot.git/blob - board/micronas/vct/dcgu.c
2 * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
4 * Original Author Guenter Gebhardt
5 * Copyright (C) 2006 Micronas GmbH
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/errno.h>
15 int dcgu_set_clk_switch(enum dcgu_hw_module module
, enum dcgu_switch setup
)
18 union dcgu_clk_en1 en1
;
19 union dcgu_clk_en2 en2
;
29 printf("%s:%i:Invalid clock switch: %i\n", __FILE__
, __LINE__
,
34 if (module
== DCGU_HW_MODULE_CPU
)
35 en2
.reg
= reg_read(DCGU_CLK_EN2(DCGU_BASE
));
37 en1
.reg
= reg_read(DCGU_CLK_EN1(DCGU_BASE
));
40 case DCGU_HW_MODULE_MSMC
:
41 en1
.bits
.en_clkmsmc
= enable
;
43 case DCGU_HW_MODULE_SSI_S
:
44 en1
.bits
.en_clkssi_s
= enable
;
46 case DCGU_HW_MODULE_SSI_M
:
47 en1
.bits
.en_clkssi_m
= enable
;
49 case DCGU_HW_MODULE_SMC
:
50 en1
.bits
.en_clksmc
= enable
;
52 case DCGU_HW_MODULE_EBI
:
53 en1
.bits
.en_clkebi
= enable
;
55 case DCGU_HW_MODULE_USB_PLL
:
56 en1
.bits
.en_usbpll
= enable
;
58 case DCGU_HW_MODULE_USB_60
:
59 en1
.bits
.en_clkusb60
= enable
;
61 case DCGU_HW_MODULE_USB_24
:
62 en1
.bits
.en_clkusb24
= enable
;
64 case DCGU_HW_MODULE_UART_2
:
65 en1
.bits
.en_clkuart2
= enable
;
67 case DCGU_HW_MODULE_UART_1
:
68 en1
.bits
.en_clkuart1
= enable
;
70 case DCGU_HW_MODULE_PERI
:
71 en1
.bits
.en_clkperi20
= enable
;
73 case DCGU_HW_MODULE_CPU
:
74 en2
.bits
.en_clkcpu
= enable
;
76 case DCGU_HW_MODULE_I2S
:
77 en1
.bits
.en_clk_i2s_dly
= enable
;
79 case DCGU_HW_MODULE_ABP_SCC
:
80 en1
.bits
.en_clk_scc_abp
= enable
;
82 case DCGU_HW_MODULE_SPDIF
:
83 en1
.bits
.en_clk_dtv_spdo
= enable
;
85 case DCGU_HW_MODULE_AD
:
86 en1
.bits
.en_clkad
= enable
;
88 case DCGU_HW_MODULE_MVD
:
89 en1
.bits
.en_clkmvd
= enable
;
91 case DCGU_HW_MODULE_TSD
:
92 en1
.bits
.en_clktsd
= enable
;
94 case DCGU_HW_MODULE_GA
:
95 en1
.bits
.en_clkga
= enable
;
97 case DCGU_HW_MODULE_DVP
:
98 en1
.bits
.en_clkdvp
= enable
;
100 case DCGU_HW_MODULE_MR2
:
101 en1
.bits
.en_clkmr2
= enable
;
103 case DCGU_HW_MODULE_MR1
:
104 en1
.bits
.en_clkmr1
= enable
;
107 printf("%s:%i:Invalid hardware module: %i\n", __FILE__
,
113 * The reg_read() following the reg_write() below forces the write to
114 * be really done on the bus.
115 * Otherwise the clock may not be switched on when this API function
116 * returns, which may cause an bus error if a registers of the hardware
117 * module connected to the clock is accessed.
119 if (module
== DCGU_HW_MODULE_CPU
) {
120 reg_write(DCGU_CLK_EN2(DCGU_BASE
), en2
.reg
);
121 en2
.reg
= reg_read(DCGU_CLK_EN2(DCGU_BASE
));
123 reg_write(DCGU_CLK_EN1(DCGU_BASE
), en1
.reg
);
124 en1
.reg
= reg_read(DCGU_CLK_EN1(DCGU_BASE
));
130 int dcgu_set_reset_switch(enum dcgu_hw_module module
, enum dcgu_switch setup
)
132 union dcgu_reset_unit1 val
;
139 case DCGU_SWITCH_OFF
:
143 printf("%s:%i:Invalid reset switch: %i\n", __FILE__
, __LINE__
,
148 val
.reg
= reg_read(DCGU_RESET_UNIT1(DCGU_BASE
));
150 case DCGU_HW_MODULE_MSMC
:
151 val
.bits
.swreset_clkmsmc
= enable
;
153 case DCGU_HW_MODULE_SSI_S
:
154 val
.bits
.swreset_clkssi_s
= enable
;
156 case DCGU_HW_MODULE_SSI_M
:
157 val
.bits
.swreset_clkssi_m
= enable
;
159 case DCGU_HW_MODULE_SMC
:
160 val
.bits
.swreset_clksmc
= enable
;
162 case DCGU_HW_MODULE_EBI
:
163 val
.bits
.swreset_clkebi
= enable
;
165 case DCGU_HW_MODULE_USB_60
:
166 val
.bits
.swreset_clkusb60
= enable
;
168 case DCGU_HW_MODULE_USB_24
:
169 val
.bits
.swreset_clkusb24
= enable
;
171 case DCGU_HW_MODULE_UART_2
:
172 val
.bits
.swreset_clkuart2
= enable
;
174 case DCGU_HW_MODULE_UART_1
:
175 val
.bits
.swreset_clkuart1
= enable
;
177 case DCGU_HW_MODULE_PWM
:
178 val
.bits
.swreset_pwm
= enable
;
180 case DCGU_HW_MODULE_GPT
:
181 val
.bits
.swreset_gpt
= enable
;
183 case DCGU_HW_MODULE_I2C2
:
184 val
.bits
.swreset_i2c2
= enable
;
186 case DCGU_HW_MODULE_I2C1
:
187 val
.bits
.swreset_i2c1
= enable
;
189 case DCGU_HW_MODULE_GPIO2
:
190 val
.bits
.swreset_gpio2
= enable
;
192 case DCGU_HW_MODULE_GPIO1
:
193 val
.bits
.swreset_gpio1
= enable
;
195 case DCGU_HW_MODULE_CPU
:
196 val
.bits
.swreset_clkcpu
= enable
;
198 case DCGU_HW_MODULE_I2S
:
199 val
.bits
.swreset_clk_i2s_dly
= enable
;
201 case DCGU_HW_MODULE_ABP_SCC
:
202 val
.bits
.swreset_clk_scc_abp
= enable
;
204 case DCGU_HW_MODULE_SPDIF
:
205 val
.bits
.swreset_clk_dtv_spdo
= enable
;
207 case DCGU_HW_MODULE_AD
:
208 val
.bits
.swreset_clkad
= enable
;
210 case DCGU_HW_MODULE_MVD
:
211 val
.bits
.swreset_clkmvd
= enable
;
213 case DCGU_HW_MODULE_TSD
:
214 val
.bits
.swreset_clktsd
= enable
;
216 case DCGU_HW_MODULE_TSIO
:
217 val
.bits
.swreset_clktsio
= enable
;
219 case DCGU_HW_MODULE_GA
:
220 val
.bits
.swreset_clkga
= enable
;
222 case DCGU_HW_MODULE_MPC
:
223 val
.bits
.swreset_clkmpc
= enable
;
225 case DCGU_HW_MODULE_CVE
:
226 val
.bits
.swreset_clkcve
= enable
;
228 case DCGU_HW_MODULE_DVP
:
229 val
.bits
.swreset_clkdvp
= enable
;
231 case DCGU_HW_MODULE_MR2
:
232 val
.bits
.swreset_clkmr2
= enable
;
234 case DCGU_HW_MODULE_MR1
:
235 val
.bits
.swreset_clkmr1
= enable
;
238 printf("%s:%i:Invalid hardware module: %i\n", __FILE__
,
242 reg_write(DCGU_RESET_UNIT1(DCGU_BASE
), val
.reg
);