board/micronas/vct/top.c

   1 /*
   2  * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
   3  *
   4  * Copyright (C) 2006 Micronas GmbH
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include "vct.h"
  11
  12 typedef union _TOP_PINMUX_t
  13 {
  14         u32 reg;
  15         struct {
  16                 u32 res         : 24;   /* reserved             */
  17                 u32 drive       :  2;   /* Driver strength      */
  18                 u32 slew        :  1;   /* Slew rate            */
  19                 u32 strig       :  1;   /* Schmitt trigger input*/
  20                 u32 pu_pd       :  2;   /* Pull up/ pull down   */
  21                 u32 funsel      :  2;   /* Pin function         */
  22         } Bits;
  23 } TOP_PINMUX_t;
  24
  25 #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
  26
  27 static TOP_PINMUX_t top_read_pin(int pin)
  28 {
  29         TOP_PINMUX_t reg;
  30
  31         switch (pin) {
  32         case 2:
  33         case 3:
  34         case 6:
  35         case 9:
  36                 reg.reg = 0xdeadbeef;
  37                 break;
  38         case 4:
  39                 reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE));
  40                 break;
  41         case 5:
  42                 reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE));
  43                 break;
  44         case 7:
  45                 reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE));
  46                 break;
  47         case 8:
  48                 reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE));
  49                 break;
  50         case 10:
  51         case 11:
  52         case 12:
  53         case 13:
  54         case 14:
  55         case 15:
  56         case 16:
  57                 reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
  58                                    ((pin - 10) * 4));
  59                 break;
  60         default:
  61                 reg.reg = reg_read(TOP_BASE + (pin * 4));
  62                 break;
  63         }
  64
  65         return reg;
  66 }
  67
  68 static void top_write_pin(int pin, TOP_PINMUX_t reg)
  69 {
  70
  71         switch (pin) {
  72         case 4:
  73                 reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg);
  74                 break;
  75         case 5:
  76                 reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg);
  77                 break;
  78         case 7:
  79                 reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg);
  80                 break;
  81         case 8:
  82                 reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg);
  83                 break;
  84         case 10:
  85         case 11:
  86         case 12:
  87         case 13:
  88         case 14:
  89         case 15:
  90         case 16:
  91                 reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
  92                           ((pin - 10) * 4), reg.reg);
  93                 break;
  94         default:
  95                 reg_write(TOP_BASE + (pin * 4), reg.reg);
  96                 break;
  97         }
  98 }
  99
 100 int top_set_pin(int pin, int func)
 101 {
 102         TOP_PINMUX_t reg;
 103
 104         /* check global range */
 105         if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3))
 106                 return -1;  /* pin number or function out of valid range */
 107
 108         /* check undefined values; */
 109         if ((pin == 2) || (pin == 3) || (pin == 6) || (pin == 9))
 110                 return -1;  /* pin number out of valid range */
 111
 112         reg = top_read_pin(pin);
 113         reg.Bits.funsel = func;
 114         top_write_pin(pin, reg);
 115
 116         return 0;
 117 }
 118
 119 #endif
 120
 121 #if defined(CONFIG_VCT_PLATINUMAVC)
 122
 123 int top_set_pin(int pin, int func)
 124 {
 125         TOP_PINMUX_t reg;
 126
 127         /* check global range */
 128         if ((pin < 0) || (pin > 158))
 129                 return -1;      /* pin number or function out of valid range */
 130
 131         reg.reg = reg_read(TOP_BASE + (pin * 4));
 132         reg.Bits.funsel = func;
 133         reg_write(TOP_BASE + (pin * 4), reg.reg);
 134
 135         return 0;
 136 }
 137
 138 #endif
 139
 140 void vct_pin_mux_initialize(void)
 141 {
 142 #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
 143         top_set_pin(34, 01);    /* EBI_CS0      */
 144         top_set_pin(33, 01);    /* EBI_CS1      */
 145         top_set_pin(32, 01);    /* EBI_CS2      */
 146         top_set_pin(100, 02);   /* EBI_CS3      */
 147         top_set_pin(101, 02);   /* EBI_CS4      */
 148         top_set_pin(102, 02);   /* EBI_CS5      */
 149         top_set_pin(103, 02);   /* EBI_CS6      */
 150         top_set_pin(104, 02);   /* EBI_CS7      top_set_pin(104,03); EBI_GENIO3 */
 151         top_set_pin(35, 01);    /* EBI_ALE      */
 152         top_set_pin(36, 01);    /* EBI_ADDR15   */
 153         top_set_pin(37, 01);    /* EBI_ADDR14   top_set_pin(78,03); EBI_ADDR14 */
 154         top_set_pin(38, 01);    /* EBI_ADDR13   */
 155         top_set_pin(39, 01);    /* EBI_ADDR12   */
 156         top_set_pin(40, 01);    /* EBI_ADDR11   */
 157         top_set_pin(41, 01);    /* EBI_ADDR10   */
 158         top_set_pin(42, 01);    /* EBI_ADDR9    */
 159         top_set_pin(43, 01);    /* EBI_ADDR8    */
 160         top_set_pin(44, 01);    /* EBI_ADDR7    */
 161         top_set_pin(45, 01);    /* EBI_ADDR6    */
 162         top_set_pin(46, 01);    /* EBI_ADDR5    */
 163         top_set_pin(47, 01);    /* EBI_ADDR4    */
 164         top_set_pin(48, 01);    /* EBI_ADDR3    */
 165         top_set_pin(49, 01);    /* EBI_ADDR2    */
 166         top_set_pin(50, 01);    /* EBI_ADDR1    */
 167         top_set_pin(51, 01);    /* EBI_ADDR0    */
 168         top_set_pin(52, 01);    /* EBI_DIR      */
 169         top_set_pin(53, 01);    /* EBI_DAT15    top_set_pin(81,01); EBI_DAT15 */
 170         top_set_pin(54, 01);    /* EBI_DAT14    top_set_pin(82,01); EBI_DAT14 */
 171         top_set_pin(55, 01);    /* EBI_DAT13    top_set_pin(83,01); EBI_DAT13 */
 172         top_set_pin(56, 01);    /* EBI_DAT12    top_set_pin(84,01); EBI_DAT12 */
 173         top_set_pin(57, 01);    /* EBI_DAT11    top_set_pin(85,01); EBI_DAT11 */
 174         top_set_pin(58, 01);    /* EBI_DAT10    top_set_pin(86,01); EBI_DAT10 */
 175         top_set_pin(59, 01);    /* EBI_DAT9     top_set_pin(87,01); EBI_DAT9 */
 176         top_set_pin(60, 01);    /* EBI_DAT8     top_set_pin(88,01); EBI_DAT8 */
 177         top_set_pin(61, 01);    /* EBI_DAT7     */
 178         top_set_pin(62, 01);    /* EBI_DAT6     */
 179         top_set_pin(63, 01);    /* EBI_DAT5     */
 180         top_set_pin(64, 01);    /* EBI_DAT4     */
 181         top_set_pin(65, 01);    /* EBI_DAT3     */
 182         top_set_pin(66, 01);    /* EBI_DAT2     */
 183         top_set_pin(67, 01);    /* EBI_DAT1     */
 184         top_set_pin(68, 01);    /* EBI_DAT0     */
 185         top_set_pin(69, 01);    /* EBI_IORD     */
 186         top_set_pin(70, 01);    /* EBI_IOWR     */
 187         top_set_pin(71, 01);    /* EBI_WE       */
 188         top_set_pin(72, 01);    /* EBI_OE       */
 189         top_set_pin(73, 01);    /* EBI_IORDY    */
 190         top_set_pin(95, 02);    /* EBI_EBI_DMACK*/
 191         top_set_pin(112, 02);   /* EBI_IRQ0     */
 192         top_set_pin(111, 02);   /* EBI_IRQ1     top_set_pin(111,03); EBI_DMARQ */
 193         top_set_pin(107, 02);   /* EBI_IRQ2     */
 194         top_set_pin(108, 02);   /* EBI_IRQ3     */
 195         top_set_pin(30, 01);    /* EBI_GENIO1   top_set_pin(99,03); EBI_GENIO1 */
 196         top_set_pin(31, 01);    /* EBI_GENIO2   top_set_pin(98,03); EBI_GENIO2 */
 197         top_set_pin(105, 02);   /* EBI_GENIO3   top_set_pin(104,03); EBI_GENIO3 */
 198         top_set_pin(106, 02);   /* EBI_GENIO4   top_set_pin(144,02); EBI_GENIO4 */
 199         top_set_pin(109, 02);   /* EBI_GENIO5   top_set_pin(142,02); EBI_GENIO5 */
 200         top_set_pin(110, 02);   /* EBI_BURST_CLK        */
 201 #endif
 202
 203 #if defined(CONFIG_VCT_PLATINUMAVC)
 204         top_set_pin(19, 01);    /* EBI_CS0      */
 205         top_set_pin(18, 01);    /* EBI_CS1      */
 206         top_set_pin(17, 01);    /* EBI_CS2      */
 207         top_set_pin(92, 02);    /* EBI_CS3      */
 208         top_set_pin(93, 02);    /* EBI_CS4      */
 209         top_set_pin(95, 02);    /* EBI_CS6      */
 210         top_set_pin(96, 02);    /* EBI_CS7      top_set_pin(104,03); EBI_GENIO3 */
 211         top_set_pin(20, 01);    /* EBI_ALE      */
 212         top_set_pin(21, 01);    /* EBI_ADDR15   */
 213         top_set_pin(22, 01);    /* EBI_ADDR14   top_set_pin(78,03); EBI_ADDR14 */
 214         top_set_pin(23, 01);    /* EBI_ADDR13   */
 215         top_set_pin(24, 01);    /* EBI_ADDR12   */
 216         top_set_pin(25, 01);    /* EBI_ADDR11   */
 217         top_set_pin(26, 01);    /* EBI_ADDR10   */
 218         top_set_pin(27, 01);    /* EBI_ADDR9    */
 219         top_set_pin(28, 01);    /* EBI_ADDR8    */
 220         top_set_pin(29, 01);    /* EBI_ADDR7    */
 221         top_set_pin(30, 01);    /* EBI_ADDR6    */
 222         top_set_pin(31, 01);    /* EBI_ADDR5    */
 223         top_set_pin(32, 01);    /* EBI_ADDR4    */
 224         top_set_pin(33, 01);    /* EBI_ADDR3    */
 225         top_set_pin(34, 01);    /* EBI_ADDR2    */
 226         top_set_pin(35, 01);    /* EBI_ADDR1    */
 227         top_set_pin(36, 01);    /* EBI_ADDR0    */
 228         top_set_pin(37, 01);    /* EBI_DIR      */
 229         top_set_pin(38, 01);    /* EBI_DAT15    top_set_pin(81,01); EBI_DAT15 */
 230         top_set_pin(39, 01);    /* EBI_DAT14    top_set_pin(82,01); EBI_DAT14 */
 231         top_set_pin(40, 01);    /* EBI_DAT13    top_set_pin(83,01); EBI_DAT13 */
 232         top_set_pin(41, 01);    /* EBI_DAT12    top_set_pin(84,01); EBI_DAT12 */
 233         top_set_pin(42, 01);    /* EBI_DAT11    top_set_pin(85,01); EBI_DAT11 */
 234         top_set_pin(43, 01);    /* EBI_DAT10    top_set_pin(86,01); EBI_DAT10 */
 235         top_set_pin(44, 01);    /* EBI_DAT9     top_set_pin(87,01); EBI_DAT9 */
 236         top_set_pin(45, 01);    /* EBI_DAT8     top_set_pin(88,01); EBI_DAT8 */
 237         top_set_pin(46, 01);    /* EBI_DAT7     */
 238         top_set_pin(47, 01);    /* EBI_DAT6     */
 239         top_set_pin(48, 01);    /* EBI_DAT5     */
 240         top_set_pin(49, 01);    /* EBI_DAT4     */
 241         top_set_pin(50, 01);    /* EBI_DAT3     */
 242         top_set_pin(51, 01);    /* EBI_DAT2     */
 243         top_set_pin(52, 01);    /* EBI_DAT1     */
 244         top_set_pin(53, 01);    /* EBI_DAT0     */
 245         top_set_pin(54, 01);    /* EBI_IORD     */
 246         top_set_pin(55, 01);    /* EBI_IOWR     */
 247         top_set_pin(56, 01);    /* EBI_WE       */
 248         top_set_pin(57, 01);    /* EBI_OE       */
 249         top_set_pin(58, 01);    /* EBI_IORDY    */
 250         top_set_pin(87, 02);    /* EBI_EBI_DMACK*/
 251         top_set_pin(106, 02);   /* EBI_IRQ0     */
 252         top_set_pin(105, 02);   /* EBI_IRQ1     top_set_pin(111,03); EBI_DMARQ */
 253         top_set_pin(101, 02);   /* EBI_IRQ2     */
 254         top_set_pin(102, 02);   /* EBI_IRQ3     */
 255         top_set_pin(15, 01);    /* EBI_GENIO1   top_set_pin(99,03); EBI_GENIO1 */
 256         top_set_pin(16, 01);    /* EBI_GENIO2   top_set_pin(98,03); EBI_GENIO2 */
 257         top_set_pin(99, 02);    /* EBI_GENIO3   top_set_pin(104,03); EBI_GENIO3 */
 258         top_set_pin(100, 02);   /* EBI_GENIO4   top_set_pin(144,02); EBI_GENIO4 */
 259         top_set_pin(103, 02);   /* EBI_GENIO5   top_set_pin(142,02); EBI_GENIO5 */
 260         top_set_pin(104, 02);   /* EBI_BURST_CLK        */
 261 #endif
 262
 263         /* I2C: Configure I2C-2 as GPIO to enable soft-i2c */
 264         top_set_pin(0, 2);      /* SCL2 on GPIO 11 */
 265         top_set_pin(1, 2);      /* SDA2 on GPIO 10 */
 266
 267         /* UART pins */
 268 #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
 269         top_set_pin(141, 1);
 270         top_set_pin(143, 1);
 271 #endif
 272 #if defined(CONFIG_VCT_PLATINUMAVC)
 273         top_set_pin(107, 1);
 274         top_set_pin(109, 1);
 275 #endif
 276 }