board/mpc8540eval/mpc8540eval.c

   1 /*
   2  * (C) Copyright 2002,2003, Motorola Inc.
   3  * Xianghua Xiao, (X.Xiao@motorola.com)
   4  *
   5  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <netdev.h>
  28 #include <asm/processor.h>
  29 #include <asm/mmu.h>
  30 #include <asm/immap_85xx.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <spd_sdram.h>
  33
  34 long int fixed_sdram (void);
  35
  36 int board_pre_init (void)
  37 {
  38 #if defined(CONFIG_PCI)
  39         volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
  40
  41         pci->peer &= 0xffffffdf; /* disable master abort */
  42 #endif
  43         return 0;
  44 }
  45
  46 int checkboard (void)
  47 {
  48         sys_info_t sysinfo;
  49
  50         get_sys_info (&sysinfo);
  51
  52         printf ("Board: Freescale MPC8540EVAL Board\n");
  53         printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
  54         printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
  55         printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
  56         if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
  57                 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
  58                 printf ("\tLBC: %lu MHz\n",
  59                         sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f));
  60         } else {
  61                 printf("\tLBC: unknown\n");
  62         }
  63         printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
  64         return (0);
  65 }
  66
  67 phys_size_t initdram (int board_type)
  68 {
  69         long dram_size = 0;
  70
  71 #if !defined(CONFIG_RAM_AS_FLASH)
  72         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  73         sys_info_t sysinfo;
  74         uint temp_lbcdll = 0;
  75 #endif
  76 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
  77         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  78 #endif
  79
  80 #if defined(CONFIG_DDR_DLL)
  81         uint temp_ddrdll = 0;
  82
  83         /* Work around to stabilize DDR DLL */
  84         temp_ddrdll = gur->ddrdllcr;
  85         gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
  86         asm("sync;isync;msync");
  87 #endif
  88
  89 #if defined(CONFIG_SPD_EEPROM)
  90         dram_size = fsl_ddr_sdram();
  91         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  92         dram_size *= 0x100000;
  93 #else
  94         dram_size = fixed_sdram ();
  95 #endif
  96
  97 #if defined(CONFIG_SYS_RAMBOOT)
  98         return dram_size;
  99 #endif
 100
 101 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
 102         get_sys_info(&sysinfo);
 103         /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
 104         if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
 105                 lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
 106         } else {
 107                 lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
 108                 udelay(200);
 109                 temp_lbcdll = gur->lbcdllcr;
 110                 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 111                 asm("sync;isync;msync");
 112         }
 113         lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
 114         lbc->br2 = CONFIG_SYS_BR2_PRELIM;
 115         lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 116         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 117         asm("sync");
 118         * (ulong *)0 = 0x000000ff;
 119         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
 120         asm("sync");
 121         * (ulong *)0 = 0x000000ff;
 122         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
 123         asm("sync");
 124         * (ulong *)0 = 0x000000ff;
 125         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 126         asm("sync");
 127         * (ulong *)0 = 0x000000ff;
 128         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
 129         asm("sync");
 130         lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 131         asm("sync");
 132         lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 133         asm("sync");
 134 #endif
 135
 136 #if defined(CONFIG_DDR_ECC)
 137         {
 138                 /* Initialize all of memory for ECC, then
 139                  * enable errors */
 140                 uint *p = 0;
 141                 uint i = 0;
 142                 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 143                 dma_init();
 144                 for (*p = 0; p < (uint *)(8 * 1024); p++) {
 145                         if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
 146                         *p = (unsigned int)0xdeadbeef;
 147                         if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
 148                 }
 149
 150                 /* 8K */
 151                 dma_xfer((uint *)0x2000,0x2000,(uint *)0);
 152                 /* 16K */
 153                 dma_xfer((uint *)0x4000,0x4000,(uint *)0);
 154                 /* 32K */
 155                 dma_xfer((uint *)0x8000,0x8000,(uint *)0);
 156                 /* 64K */
 157                 dma_xfer((uint *)0x10000,0x10000,(uint *)0);
 158                 /* 128k */
 159                 dma_xfer((uint *)0x20000,0x20000,(uint *)0);
 160                 /* 256k */
 161                 dma_xfer((uint *)0x40000,0x40000,(uint *)0);
 162                 /* 512k */
 163                 dma_xfer((uint *)0x80000,0x80000,(uint *)0);
 164                 /* 1M */
 165                 dma_xfer((uint *)0x100000,0x100000,(uint *)0);
 166                 /* 2M */
 167                 dma_xfer((uint *)0x200000,0x200000,(uint *)0);
 168                 /* 4M */
 169                 dma_xfer((uint *)0x400000,0x400000,(uint *)0);
 170
 171                 for (i = 1; i < dram_size / 0x800000; i++) {
 172                         dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
 173                 }
 174
 175                 /* Enable errors for ECC */
 176                 ddr->err_disable = 0x00000000;
 177                 asm("sync;isync;msync");
 178         }
 179 #endif
 180
 181         return dram_size;
 182 }
 183
 184 #if defined(CONFIG_SYS_DRAM_TEST)
 185 int testdram (void)
 186 {
 187         uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
 188         uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 189         uint *p;
 190
 191         printf("SDRAM test phase 1:\n");
 192         for (p = pstart; p < pend; p++)
 193                 *p = 0xaaaaaaaa;
 194
 195         for (p = pstart; p < pend; p++) {
 196                 if (*p != 0xaaaaaaaa) {
 197                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 198                         return 1;
 199                 }
 200         }
 201
 202         printf("SDRAM test phase 2:\n");
 203         for (p = pstart; p < pend; p++)
 204                 *p = 0x55555555;
 205
 206         for (p = pstart; p < pend; p++) {
 207                 if (*p != 0x55555555) {
 208                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 209                         return 1;
 210                 }
 211         }
 212
 213         printf("SDRAM test passed.\n");
 214         return 0;
 215 }
 216 #endif
 217
 218 #if !defined(CONFIG_SPD_EEPROM)
 219 /*************************************************************************
 220  *  fixed sdram init -- doesn't use serial presence detect.
 221  ************************************************************************/
 222 long int fixed_sdram (void)
 223 {
 224 #ifndef CONFIG_SYS_RAMBOOT
 225         volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 226
 227         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 228         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 229         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 230         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 231         ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
 232         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 233 #if defined (CONFIG_DDR_ECC)
 234         ddr->err_disable = 0x0000000D;
 235         ddr->err_sbe = 0x00ff0000;
 236 #endif
 237         asm("sync;isync;msync");
 238         udelay(500);
 239 #if defined (CONFIG_DDR_ECC)
 240         /* Enable ECC checking */
 241         ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 242 #else
 243         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 244 #endif
 245         asm("sync; isync; msync");
 246         udelay(500);
 247 #endif
 248         return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
 249 }
 250 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 251
 252 int board_eth_init(bd_t *bis)
 253 {
 254         /*
 255          * This board either has PCI NICs or uses the CPU's TSECs
 256          * pci_eth_init() will return 0 if no NICs found, so in that case
 257          * returning -1 will force cpu_eth_init() to be called.
 258          */
 259         int num = pci_eth_init(bis);
 260         return (num <= 0 ? -1 : num);
 261 }