board/mpc8540eval/mpc8540eval.c

   1 /*
   2  * (C) Copyright 2002,2003, Motorola Inc.
   3  * Xianghua Xiao, (X.Xiao@motorola.com)
   4  *
   5  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/processor.h>
  28 #include <asm/immap_85xx.h>
  29 #include <spd.h>
  30
  31 extern long int spd_sdram (void);
  32
  33 long int fixed_sdram (void);
  34
  35 int board_pre_init (void)
  36 {
  37 #if defined(CONFIG_PCI)
  38         volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
  39
  40         pci->peer &= 0xffffffdf; /* disable master abort */
  41 #endif
  42         return 0;
  43 }
  44
  45 int checkboard (void)
  46 {
  47         sys_info_t sysinfo;
  48
  49         get_sys_info (&sysinfo);
  50
  51         printf ("Board: Freescale MPC8540EVAL Board\n");
  52         printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
  53         printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
  54         printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
  55         if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
  56                 || (CFG_LBC_LCRR & 0x0f) == 8) {
  57                 printf ("\tLBC: %lu MHz\n",
  58                         sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
  59         } else {
  60                 printf("\tLBC: unknown\n");
  61         }
  62         printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
  63         return (0);
  64 }
  65
  66 long int initdram (int board_type)
  67 {
  68         long dram_size = 0;
  69         extern long spd_sdram (void);
  70 #if !defined(CONFIG_RAM_AS_FLASH)
  71         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
  72         sys_info_t sysinfo;
  73         uint temp_lbcdll = 0;
  74 #endif
  75 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
  76         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  77 #endif
  78
  79 #if defined(CONFIG_DDR_DLL)
  80         uint temp_ddrdll = 0;
  81
  82         /* Work around to stabilize DDR DLL */
  83         temp_ddrdll = gur->ddrdllcr;
  84         gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
  85         asm("sync;isync;msync");
  86 #endif
  87
  88 #if defined(CONFIG_SPD_EEPROM)
  89         dram_size = spd_sdram ();
  90 #else
  91         dram_size = fixed_sdram ();
  92 #endif
  93
  94 #if defined(CFG_RAMBOOT)
  95         return dram_size;
  96 #endif
  97
  98 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
  99         get_sys_info(&sysinfo);
 100         /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
 101         if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
 102                 lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
 103         } else {
 104                 lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
 105                 udelay(200);
 106                 temp_lbcdll = gur->lbcdllcr;
 107                 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 108                 asm("sync;isync;msync");
 109         }
 110         lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
 111         lbc->br2 = CFG_BR2_PRELIM;
 112         lbc->lbcr = CFG_LBC_LBCR;
 113         lbc->lsdmr = CFG_LBC_LSDMR_1;
 114         asm("sync");
 115         * (ulong *)0 = 0x000000ff;
 116         lbc->lsdmr = CFG_LBC_LSDMR_2;
 117         asm("sync");
 118         * (ulong *)0 = 0x000000ff;
 119         lbc->lsdmr = CFG_LBC_LSDMR_3;
 120         asm("sync");
 121         * (ulong *)0 = 0x000000ff;
 122         lbc->lsdmr = CFG_LBC_LSDMR_4;
 123         asm("sync");
 124         * (ulong *)0 = 0x000000ff;
 125         lbc->lsdmr = CFG_LBC_LSDMR_5;
 126         asm("sync");
 127         lbc->lsrt = CFG_LBC_LSRT;
 128         asm("sync");
 129         lbc->mrtpr = CFG_LBC_MRTPR;
 130         asm("sync");
 131 #endif
 132
 133 #if defined(CONFIG_DDR_ECC)
 134         {
 135                 /* Initialize all of memory for ECC, then
 136                  * enable errors */
 137                 uint *p = 0;
 138                 uint i = 0;
 139                 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 140                 dma_init();
 141                 for (*p = 0; p < (uint *)(8 * 1024); p++) {
 142                         if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
 143                         *p = (unsigned int)0xdeadbeef;
 144                         if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
 145                 }
 146
 147                 /* 8K */
 148                 dma_xfer((uint *)0x2000,0x2000,(uint *)0);
 149                 /* 16K */
 150                 dma_xfer((uint *)0x4000,0x4000,(uint *)0);
 151                 /* 32K */
 152                 dma_xfer((uint *)0x8000,0x8000,(uint *)0);
 153                 /* 64K */
 154                 dma_xfer((uint *)0x10000,0x10000,(uint *)0);
 155                 /* 128k */
 156                 dma_xfer((uint *)0x20000,0x20000,(uint *)0);
 157                 /* 256k */
 158                 dma_xfer((uint *)0x40000,0x40000,(uint *)0);
 159                 /* 512k */
 160                 dma_xfer((uint *)0x80000,0x80000,(uint *)0);
 161                 /* 1M */
 162                 dma_xfer((uint *)0x100000,0x100000,(uint *)0);
 163                 /* 2M */
 164                 dma_xfer((uint *)0x200000,0x200000,(uint *)0);
 165                 /* 4M */
 166                 dma_xfer((uint *)0x400000,0x400000,(uint *)0);
 167
 168                 for (i = 1; i < dram_size / 0x800000; i++) {
 169                         dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
 170                 }
 171
 172                 /* Enable errors for ECC */
 173                 ddr->err_disable = 0x00000000;
 174                 asm("sync;isync;msync");
 175         }
 176 #endif
 177
 178         return dram_size;
 179 }
 180
 181 #if defined(CFG_DRAM_TEST)
 182 int testdram (void)
 183 {
 184         uint *pstart = (uint *) CFG_MEMTEST_START;
 185         uint *pend = (uint *) CFG_MEMTEST_END;
 186         uint *p;
 187
 188         printf("SDRAM test phase 1:\n");
 189         for (p = pstart; p < pend; p++)
 190                 *p = 0xaaaaaaaa;
 191
 192         for (p = pstart; p < pend; p++) {
 193                 if (*p != 0xaaaaaaaa) {
 194                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 195                         return 1;
 196                 }
 197         }
 198
 199         printf("SDRAM test phase 2:\n");
 200         for (p = pstart; p < pend; p++)
 201                 *p = 0x55555555;
 202
 203         for (p = pstart; p < pend; p++) {
 204                 if (*p != 0x55555555) {
 205                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 206                         return 1;
 207                 }
 208         }
 209
 210         printf("SDRAM test passed.\n");
 211         return 0;
 212 }
 213 #endif
 214
 215 #if !defined(CONFIG_SPD_EEPROM)
 216 /*************************************************************************
 217  *  fixed sdram init -- doesn't use serial presence detect.
 218  ************************************************************************/
 219 long int fixed_sdram (void)
 220 {
 221 #ifndef CFG_RAMBOOT
 222         volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 223
 224         ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 225         ddr->cs0_config = CFG_DDR_CS0_CONFIG;
 226         ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 227         ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
 228         ddr->sdram_mode = CFG_DDR_MODE;
 229         ddr->sdram_interval = CFG_DDR_INTERVAL;
 230 #if defined (CONFIG_DDR_ECC)
 231         ddr->err_disable = 0x0000000D;
 232         ddr->err_sbe = 0x00ff0000;
 233 #endif
 234         asm("sync;isync;msync");
 235         udelay(500);
 236 #if defined (CONFIG_DDR_ECC)
 237         /* Enable ECC checking */
 238         ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
 239 #else
 240         ddr->sdram_cfg = CFG_DDR_CONTROL;
 241 #endif
 242         asm("sync; isync; msync");
 243         udelay(500);
 244 #endif
 245         return (CFG_SDRAM_SIZE * 1024 * 1024);
 246 }
 247 #endif  /* !defined(CONFIG_SPD_EEPROM) */