board/mpc8560ads/mpc8560ads.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2003,Motorola Inc.
   4  * Xianghua Xiao, (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27
  28 #include <common.h>
  29 #include <pci.h>
  30 #include <asm/processor.h>
  31 #include <asm/immap_85xx.h>
  32 #include <ioports.h>
  33 #include <spd.h>
  34 #include <miiphy.h>
  35
  36 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  37 extern void ddr_enable_ecc(unsigned int dram_size);
  38 #endif
  39
  40 extern long int spd_sdram(void);
  41
  42 void local_bus_init(void);
  43 void sdram_init(void);
  44 long int fixed_sdram(void);
  45
  46
  47 /*
  48  * I/O Port configuration table
  49  *
  50  * if conf is 1, then that port pin will be configured at boot time
  51  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  52  */
  53
  54 const iop_conf_t iop_conf_tab[4][32] = {
  55
  56     /* Port A configuration */
  57     {   /*            conf ppar psor pdir podr pdat */
  58         /* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
  59         /* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
  60         /* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
  61         /* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
  62         /* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
  63         /* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
  64         /* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
  65         /* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
  66         /* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
  67         /* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
  68         /* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
  69         /* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
  70         /* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
  71         /* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
  72         /* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
  73         /* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
  74         /* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
  75         /* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
  76         /* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
  77         /* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
  78         /* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
  79         /* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
  80         /* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
  81         /* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
  82         /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  83         /* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
  84         /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  85         /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  86         /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  87         /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  88         /* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
  89         /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  90     },
  91
  92     /* Port B configuration */
  93     {   /*            conf ppar psor pdir podr pdat */
  94         /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  95         /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  96         /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  97         /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  98         /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  99         /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
 100         /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
 101         /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
 102         /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
 103         /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
 104         /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
 105         /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 106         /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 107         /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
 108         /* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
 109         /* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
 110         /* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
 111         /* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
 112         /* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
 113         /* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
 114         /* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 115         /* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 116         /* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 117         /* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 118         /* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 119         /* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 120         /* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 121         /* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 122         /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 123         /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 124         /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 125         /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 126     },
 127
 128     /* Port C */
 129     {   /*            conf ppar psor pdir podr pdat */
 130         /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 131         /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 132         /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
 133         /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
 134         /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
 135         /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 136         /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 137         /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 138         /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
 139         /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
 140         /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
 141         /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
 142         /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
 143         /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
 144         /* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 145         /* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
 146         /* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
 147         /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
 148         /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 149         /* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
 150         /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
 151         /* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
 152         /* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
 153         /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 154         /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 155         /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 156         /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 157         /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 158         /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 159         /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
 160         /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
 161         /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
 162     },
 163
 164     /* Port D */
 165     {   /*            conf ppar psor pdir podr pdat */
 166         /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
 167         /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
 168         /* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
 169         /* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
 170         /* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
 171         /* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
 172         /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 173         /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 174         /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
 175         /* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
 176         /* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
 177         /* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
 178         /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 179         /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
 180         /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 181         /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
 182         /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
 183         /* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
 184         /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 185         /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 186         /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 187         /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 188         /* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 189         /* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 190         /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 191         /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 192         /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 193         /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 194         /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 195         /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 196         /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 197         /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 198     }
 199 };
 200
 201
 202 /*
 203  * MPC8560ADS Board Status & Control Registers
 204  */
 205 typedef struct bcsr_ {
 206         volatile unsigned char bcsr0;
 207         volatile unsigned char bcsr1;
 208         volatile unsigned char bcsr2;
 209         volatile unsigned char bcsr3;
 210         volatile unsigned char bcsr4;
 211         volatile unsigned char bcsr5;
 212 } bcsr_t;
 213
 214
 215 int board_early_init_f (void)
 216 {
 217     return 0;
 218 }
 219
 220 void reset_phy (void)
 221 {
 222 #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
 223         volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
 224 #endif
 225         /* reset Giga bit Ethernet port if needed here */
 226
 227         /* reset the CPM FEC port */
 228 #if (CONFIG_ETHER_INDEX == 2)
 229         bcsr->bcsr2 &= ~FETH2_RST;
 230         udelay(2);
 231         bcsr->bcsr2 |=  FETH2_RST;
 232         udelay(1000);
 233 #elif (CONFIG_ETHER_INDEX == 3)
 234         bcsr->bcsr3 &= ~FETH3_RST;
 235         udelay(2);
 236         bcsr->bcsr3 |=  FETH3_RST;
 237         udelay(1000);
 238 #endif
 239 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
 240         miiphy_reset(0x0);      /* reset PHY */
 241         miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
 242         miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 243 #endif /* CONFIG_MII */
 244 }
 245
 246
 247 int checkboard (void)
 248 {
 249         puts("Board: ADS\n");
 250
 251 #ifdef CONFIG_PCI
 252         printf("    PCI1: 32 bit, %d MHz (compiled)\n",
 253                CONFIG_SYS_CLK_FREQ / 1000000);
 254 #else
 255         printf("    PCI1: disabled\n");
 256 #endif
 257
 258         /*
 259          * Initialize local bus.
 260          */
 261         local_bus_init();
 262
 263         return 0;
 264 }
 265
 266
 267 long int
 268 initdram(int board_type)
 269 {
 270         long dram_size = 0;
 271         extern long spd_sdram (void);
 272         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 273
 274         puts("Initializing\n");
 275
 276 #if defined(CONFIG_DDR_DLL)
 277         {
 278             volatile ccsr_gur_t *gur= &immap->im_gur;
 279             uint temp_ddrdll = 0;
 280
 281             /*
 282              * Work around to stabilize DDR DLL
 283              */
 284             temp_ddrdll = gur->ddrdllcr;
 285             gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
 286             asm("sync;isync;msync");
 287         }
 288 #endif
 289
 290 #if defined(CONFIG_SPD_EEPROM)
 291         dram_size = spd_sdram ();
 292 #else
 293         dram_size = fixed_sdram ();
 294 #endif
 295
 296 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 297         /*
 298          * Initialize and enable DDR ECC.
 299          */
 300         ddr_enable_ecc(dram_size);
 301 #endif
 302
 303         /*
 304          * Initialize SDRAM.
 305          */
 306         sdram_init();
 307
 308         puts("    DDR: ");
 309         return dram_size;
 310 }
 311
 312
 313 /*
 314  * Initialize Local Bus
 315  */
 316
 317 void
 318 local_bus_init(void)
 319 {
 320         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 321         volatile ccsr_gur_t *gur = &immap->im_gur;
 322         volatile ccsr_lbc_t *lbc = &immap->im_lbc;
 323
 324         uint clkdiv;
 325         uint lbc_hz;
 326         sys_info_t sysinfo;
 327
 328         /*
 329          * Errata LBC11.
 330          * Fix Local Bus clock glitch when DLL is enabled.
 331          *
 332          * If localbus freq is < 66Mhz, DLL bypass mode must be used.
 333          * If localbus freq is > 133Mhz, DLL can be safely enabled.
 334          * Between 66 and 133, the DLL is enabled with an override workaround.
 335          */
 336
 337         get_sys_info(&sysinfo);
 338         clkdiv = lbc->lcrr & 0x0f;
 339         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 340
 341         if (lbc_hz < 66) {
 342                 lbc->lcrr = CFG_LBC_LCRR | 0x80000000;  /* DLL Bypass */
 343
 344         } else if (lbc_hz >= 133) {
 345                 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 346
 347         } else {
 348                 /*
 349                  * On REV1 boards, need to change CLKDIV before enable DLL.
 350                  * Default CLKDIV is 8, change it to 4 temporarily.
 351                  */
 352                 uint pvr = get_pvr();
 353                 uint temp_lbcdll = 0;
 354
 355                 if (pvr == PVR_85xx_REV1) {
 356                         /* FIXME: Justify the high bit here. */
 357                         lbc->lcrr = 0x10000004;
 358                 }
 359
 360                 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
 361                 udelay(200);
 362
 363                 /*
 364                  * Sample LBC DLL ctrl reg, upshift it to set the
 365                  * override bits.
 366                  */
 367                 temp_lbcdll = gur->lbcdllcr;
 368                 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 369                 asm("sync;isync;msync");
 370         }
 371 }
 372
 373
 374 /*
 375  * Initialize SDRAM memory on the Local Bus.
 376  */
 377
 378 void
 379 sdram_init(void)
 380 {
 381         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 382         volatile ccsr_lbc_t *lbc= &immap->im_lbc;
 383         uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 384
 385         puts("    SDRAM: ");
 386         print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 387
 388         /*
 389          * Setup SDRAM Base and Option Registers
 390          */
 391         lbc->or2 = CFG_OR2_PRELIM;
 392         lbc->br2 = CFG_BR2_PRELIM;
 393         lbc->lbcr = CFG_LBC_LBCR;
 394         asm("msync");
 395
 396         lbc->lsrt = CFG_LBC_LSRT;
 397         lbc->mrtpr = CFG_LBC_MRTPR;
 398         asm("sync");
 399
 400         /*
 401          * Configure the SDRAM controller.
 402          */
 403         lbc->lsdmr = CFG_LBC_LSDMR_1;
 404         asm("sync");
 405         *sdram_addr = 0xff;
 406         ppcDcbf((unsigned long) sdram_addr);
 407         udelay(100);
 408
 409         lbc->lsdmr = CFG_LBC_LSDMR_2;
 410         asm("sync");
 411         *sdram_addr = 0xff;
 412         ppcDcbf((unsigned long) sdram_addr);
 413         udelay(100);
 414
 415         lbc->lsdmr = CFG_LBC_LSDMR_3;
 416         asm("sync");
 417         *sdram_addr = 0xff;
 418         ppcDcbf((unsigned long) sdram_addr);
 419         udelay(100);
 420
 421         lbc->lsdmr = CFG_LBC_LSDMR_4;
 422         asm("sync");
 423         *sdram_addr = 0xff;
 424         ppcDcbf((unsigned long) sdram_addr);
 425         udelay(100);
 426
 427         lbc->lsdmr = CFG_LBC_LSDMR_5;
 428         asm("sync");
 429         *sdram_addr = 0xff;
 430         ppcDcbf((unsigned long) sdram_addr);
 431         udelay(100);
 432 }
 433
 434
 435 #if defined(CFG_DRAM_TEST)
 436 int testdram (void)
 437 {
 438         uint *pstart = (uint *) CFG_MEMTEST_START;
 439         uint *pend = (uint *) CFG_MEMTEST_END;
 440         uint *p;
 441
 442         printf("SDRAM test phase 1:\n");
 443         for (p = pstart; p < pend; p++)
 444                 *p = 0xaaaaaaaa;
 445
 446         for (p = pstart; p < pend; p++) {
 447                 if (*p != 0xaaaaaaaa) {
 448                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 449                         return 1;
 450                 }
 451         }
 452
 453         printf("SDRAM test phase 2:\n");
 454         for (p = pstart; p < pend; p++)
 455                 *p = 0x55555555;
 456
 457         for (p = pstart; p < pend; p++) {
 458                 if (*p != 0x55555555) {
 459                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 460                         return 1;
 461                 }
 462         }
 463
 464         printf("SDRAM test passed.\n");
 465         return 0;
 466 }
 467 #endif
 468
 469
 470 #if !defined(CONFIG_SPD_EEPROM)
 471 /*************************************************************************
 472  *  fixed sdram init -- doesn't use serial presence detect.
 473  ************************************************************************/
 474 long int fixed_sdram (void)
 475 {
 476   #ifndef CFG_RAMBOOT
 477         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 478         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
 479
 480         ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 481         ddr->cs0_config = CFG_DDR_CS0_CONFIG;
 482         ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 483         ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
 484         ddr->sdram_mode = CFG_DDR_MODE;
 485         ddr->sdram_interval = CFG_DDR_INTERVAL;
 486     #if defined (CONFIG_DDR_ECC)
 487         ddr->err_disable = 0x0000000D;
 488         ddr->err_sbe = 0x00ff0000;
 489     #endif
 490         asm("sync;isync;msync");
 491         udelay(500);
 492     #if defined (CONFIG_DDR_ECC)
 493         /* Enable ECC checking */
 494         ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
 495     #else
 496         ddr->sdram_cfg = CFG_DDR_CONTROL;
 497     #endif
 498         asm("sync; isync; msync");
 499         udelay(500);
 500   #endif
 501         return CFG_SDRAM_SIZE * 1024 * 1024;
 502 }
 503 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 504
 505
 506 #if defined(CONFIG_PCI)
 507 /*
 508  * Initialize PCI Devices, report devices found.
 509  */
 510
 511 #ifndef CONFIG_PCI_PNP
 512 static struct pci_config_table pci_mpc85xxads_config_table[] = {
 513     { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 514       PCI_IDSEL_NUMBER, PCI_ANY_ID,
 515       pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 516                                    PCI_ENET0_MEMADDR,
 517                                    PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
 518       } },
 519     { }
 520 };
 521 #endif
 522
 523
 524 static struct pci_controller hose = {
 525 #ifndef CONFIG_PCI_PNP
 526         config_table: pci_mpc85xxads_config_table,
 527 #endif
 528 };
 529
 530 #endif  /* CONFIG_PCI */
 531
 532
 533 void
 534 pci_init_board(void)
 535 {
 536 #ifdef CONFIG_PCI
 537         extern void pci_mpc85xx_init(struct pci_controller *hose);
 538
 539         pci_mpc85xx_init(&hose);
 540 #endif /* CONFIG_PCI */
 541 }