]>
git.ipfire.org Git - people/ms/u-boot.git/blob - board/mpl/mip405/mip405.c
3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
30 * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
31 * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
32 * parameters from the datasheet are:
33 * Tclk = 7.5ns (CL = 2)
39 * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
40 * period is 10ns and the parameters needed for the Timing Register are:
41 * CASL = CL = 2 clock cycles
42 * PTA = Trp = 15ns / 10ns = 2 clock cycles
43 * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
44 * LDF = 2 clock cycles (but can be extended to meet board-level timing)
45 * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
46 * RCD = Trcd = 15ns / 10ns= 2 clock cycles
48 * The actual bit settings in the register would be:
57 * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
58 * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
59 * defined as Trc rather than Trfc.
60 * When using DIMM modules, most but not all of the required timing parameters can be read
61 * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
62 * are not available from the EEPROM
67 #include <asm/processor.h>
70 #include "../common/common_util.h"
74 DECLARE_GLOBAL_DATA_PTR
;
77 #define ENABLE_ECC /* for ecc boards */
81 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
82 #ifndef __ldiv_t_defined
84 long int quot
; /* Quotient */
85 long int rem
; /* Remainder */
87 extern ldiv_t ldiv (long int __numer
, long int __denom
);
88 # define __ldiv_t_defined 1
92 #define PLD_PART_REG PER_PLD_ADDR + 0
93 #define PLD_VERS_REG PER_PLD_ADDR + 1
94 #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
95 #define PLD_IRQ_REG PER_PLD_ADDR + 3
96 #define PLD_COM_MODE_REG PER_PLD_ADDR + 4
97 #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
99 #define MEGA_BYTE (1024*1024)
102 unsigned char boardtype
; /* Board revision and Population Options */
103 unsigned char cal
; /* cas Latency (will be programmend as cal-1) */
104 unsigned char trp
; /* datain27 in clocks */
105 unsigned char trcd
; /* datain29 in clocks */
106 unsigned char tras
; /* datain30 in clocks */
107 unsigned char tctp
; /* tras - trcd in clocks */
108 unsigned char am
; /* Address Mod (will be programmed as am-1) */
109 unsigned char sz
; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
110 unsigned char ecc
; /* if true, ecc is enabled */
112 #if defined(CONFIG_MIP405T)
113 const sdram_t sdram_table
[] = {
114 { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
115 3, /* Case Latenty = 3 */
116 3, /* trp 20ns / 7.5 ns datain[27] */
117 3, /* trcd 20ns /7.5 ns (datain[29]) */
118 6, /* tras 44ns /7.5 ns (datain[30]) */
119 4, /* tcpt 44 - 20ns = 24ns */
120 2, /* Address Mode = 2 (12x9x4) */
121 3, /* size value (32MByte) */
122 0}, /* ECC disabled */
123 { 0xff, /* terminator */
133 const sdram_t sdram_table
[] = {
134 { 0x0f, /* Rev A, 128MByte -1 Board */
135 3, /* Case Latenty = 3 */
136 3, /* trp 20ns / 7.5 ns datain[27] */
137 3, /* trcd 20ns /7.5 ns (datain[29]) */
138 6, /* tras 44ns /7.5 ns (datain[30]) */
139 4, /* tcpt 44 - 20ns = 24ns */
140 3, /* Address Mode = 3 */
142 1}, /* ECC enabled */
143 { 0x07, /* Rev A, 64MByte -2 Board */
144 3, /* Case Latenty = 3 */
145 3, /* trp 20ns / 7.5 ns datain[27] */
146 3, /* trcd 20ns /7.5 ns (datain[29]) */
147 6, /* tras 44ns /7.5 ns (datain[30]) */
148 4, /* tcpt 44 - 20ns = 24ns */
149 2, /* Address Mode = 2 */
151 1}, /* ECC enabled */
152 { 0x03, /* Rev A, 128MByte -4 Board */
153 3, /* Case Latenty = 3 */
154 3, /* trp 20ns / 7.5 ns datain[27] */
155 3, /* trcd 20ns /7.5 ns (datain[29]) */
156 6, /* tras 44ns /7.5 ns (datain[30]) */
157 4, /* tcpt 44 - 20ns = 24ns */
158 3, /* Address Mode = 3 */
160 1}, /* ECC enabled */
161 { 0x1f, /* Rev B, 128MByte -3 Board */
162 3, /* Case Latenty = 3 */
163 3, /* trp 20ns / 7.5 ns datain[27] */
164 3, /* trcd 20ns /7.5 ns (datain[29]) */
165 6, /* tras 44ns /7.5 ns (datain[30]) */
166 4, /* tcpt 44 - 20ns = 24ns */
167 3, /* Address Mode = 3 */
169 1}, /* ECC enabled */
170 { 0x2f, /* Rev C, 128MByte -3 Board */
171 3, /* Case Latenty = 3 */
172 3, /* trp 20ns / 7.5 ns datain[27] */
173 3, /* trcd 20ns /7.5 ns (datain[29]) */
174 6, /* tras 44ns /7.5 ns (datain[30]) */
175 4, /* tcpt 44 - 20ns = 24ns */
176 3, /* Address Mode = 3 */
178 1}, /* ECC enabled */
179 { 0xff, /* terminator */
188 #endif /*CONFIG_MIP405T */
189 void SDRAM_err (const char *s
)
192 (void) get_clocks ();
198 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
203 unsigned char get_board_revcfg (void)
205 out8 (PER_BOARD_ADDR
, 0);
206 return (in8 (PER_BOARD_ADDR
));
212 void write_hex (unsigned char i
)
219 serial_putc (cc
+ 55);
221 serial_putc (cc
+ 48);
224 serial_putc (cc
+ 55);
226 serial_putc (cc
+ 48);
229 void write_4hex (unsigned long val
)
231 write_hex ((unsigned char) (val
>> 24));
232 write_hex ((unsigned char) (val
>> 16));
233 write_hex ((unsigned char) (val
>> 8));
234 write_hex ((unsigned char) val
);
240 int init_sdram (void)
242 unsigned long tmp
, baseaddr
;
244 unsigned char trp_clocks
,
249 unsigned char cal_val
;
251 unsigned long sdram_tim
, sdram_bank
;
253 /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/
254 (void) get_clocks ();
258 mtdcr (ebccfga
, pb7ap
);
259 mtdcr (ebccfgd
, PLD_AP
);
260 mtdcr (ebccfga
, pb7cr
);
261 mtdcr (ebccfgd
, PLD_CR
);
262 /* THIS IS OBSOLETE */
263 /* set up the board rev reg*/
264 mtdcr (ebccfga
, pb5ap
);
265 mtdcr (ebccfgd
, BOARD_AP
);
266 mtdcr (ebccfga
, pb5cr
);
267 mtdcr (ebccfgd
, BOARD_CR
);
269 /* get all informations from PLD */
270 serial_puts ("\nPLD Part 0x");
271 bc
= in8 (PLD_PART_REG
);
273 serial_puts ("\nPLD Vers 0x");
274 bc
= in8 (PLD_VERS_REG
);
276 serial_puts ("\nBoard Rev 0x");
277 bc
= in8 (PLD_BOARD_CFG_REG
);
282 bc
= in8 (PLD_PART_REG
);
283 #if defined(CONFIG_MIP405T)
285 SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
287 if((bc
& 0x80)==0x80)
288 SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
290 /* set-up the chipselect machine */
291 mtdcr (ebccfga
, pb0cr
); /* get cs0 config reg */
292 tmp
= mfdcr (ebccfgd
);
293 if ((tmp
& 0x00002000) == 0) {
294 /* MPS Boot, set up the flash */
295 mtdcr (ebccfga
, pb1ap
);
296 mtdcr (ebccfgd
, FLASH_AP
);
297 mtdcr (ebccfga
, pb1cr
);
298 mtdcr (ebccfgd
, FLASH_CR
);
300 /* Flash boot, set up the MPS */
301 mtdcr (ebccfga
, pb1ap
);
302 mtdcr (ebccfgd
, MPS_AP
);
303 mtdcr (ebccfga
, pb1cr
);
304 mtdcr (ebccfgd
, MPS_CR
);
306 /* set up UART0 (CS2) and UART1 (CS3) */
307 mtdcr (ebccfga
, pb2ap
);
308 mtdcr (ebccfgd
, UART0_AP
);
309 mtdcr (ebccfga
, pb2cr
);
310 mtdcr (ebccfgd
, UART0_CR
);
311 mtdcr (ebccfga
, pb3ap
);
312 mtdcr (ebccfgd
, UART1_AP
);
313 mtdcr (ebccfga
, pb3cr
);
314 mtdcr (ebccfgd
, UART1_CR
);
315 bc
= in8 (PLD_BOARD_CFG_REG
);
317 serial_puts ("\nstart SDRAM Setup\n");
318 serial_puts ("\nBoard Rev: ");
323 baseaddr
= CONFIG_SYS_SDRAM_BASE
;
324 while (sdram_table
[i
].sz
!= 0xff) {
325 if (sdram_table
[i
].boardtype
== bc
)
329 if (sdram_table
[i
].boardtype
!= bc
)
330 SDRAM_err ("No SDRAM table found for this board!!!\n");
332 serial_puts (" found table ");
336 /* since the ECC initialisation needs some time,
337 * we show that we're alive
339 if (sdram_table
[i
].ecc
)
340 serial_puts ("\nInitializing SDRAM, Please stand by");
341 cal_val
= sdram_table
[i
].cal
- 1; /* Cas Latency */
342 trp_clocks
= sdram_table
[i
].trp
; /* 20ns / 7.5 ns datain[27] */
343 trcd_clocks
= sdram_table
[i
].trcd
; /* 20ns /7.5 ns (datain[29]) */
344 tras_clocks
= sdram_table
[i
].tras
; /* 44ns /7.5 ns (datain[30]) */
345 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
346 tctp_clocks
= sdram_table
[i
].tctp
; /* 44 - 20ns = 24ns */
347 /* trc_clocks is sum of trp_clocks + tras_clocks */
348 trc_clocks
= trp_clocks
+ tras_clocks
;
349 /* get SDRAM timing register */
350 mtdcr (memcfga
, mem_sdtr1
);
351 sdram_tim
= mfdcr (memcfgd
) & ~0x018FC01F;
352 /* insert CASL value */
353 sdram_tim
|= ((unsigned long) (cal_val
)) << 23;
354 /* insert PTA value */
355 sdram_tim
|= ((unsigned long) (trp_clocks
- 1)) << 18;
356 /* insert CTP value */
358 ((unsigned long) (trc_clocks
- trp_clocks
-
360 /* insert LDF (always 01) */
361 sdram_tim
|= ((unsigned long) 0x01) << 14;
362 /* insert RFTA value */
363 sdram_tim
|= ((unsigned long) (trc_clocks
- 4)) << 2;
364 /* insert RCD value */
365 sdram_tim
|= ((unsigned long) (trcd_clocks
- 1)) << 0;
367 tmp
= ((unsigned long) (sdram_table
[i
].am
- 1) << 13); /* AM = 3 */
368 /* insert SZ value; */
369 tmp
|= ((unsigned long) sdram_table
[i
].sz
<< 17);
370 /* get SDRAM bank 0 register */
371 mtdcr (memcfga
, mem_mb0cf
);
372 sdram_bank
= mfdcr (memcfgd
) & ~0xFFCEE001;
373 sdram_bank
|= (baseaddr
| tmp
| 0x01);
376 serial_puts ("sdtr: ");
377 write_4hex (sdram_tim
);
381 /* write SDRAM timing register */
382 mtdcr (memcfga
, mem_sdtr1
);
383 mtdcr (memcfgd
, sdram_tim
);
386 serial_puts ("mb0cf: ");
387 write_4hex (sdram_bank
);
391 /* write SDRAM bank 0 register */
392 mtdcr (memcfga
, mem_mb0cf
);
393 mtdcr (memcfgd
, sdram_bank
);
395 if (get_bus_freq (tmp
) > 110000000) { /* > 110MHz */
396 /* get SDRAM refresh interval register */
397 mtdcr (memcfga
, mem_rtr
);
398 tmp
= mfdcr (memcfgd
) & ~0x3FF80000;
401 /* get SDRAM refresh interval register */
402 mtdcr (memcfga
, mem_rtr
);
403 tmp
= mfdcr (memcfgd
) & ~0x3FF80000;
406 /* write SDRAM refresh interval register */
407 mtdcr (memcfga
, mem_rtr
);
408 mtdcr (memcfgd
, tmp
);
409 /* enable ECC if used */
410 #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
411 if (sdram_table
[i
].ecc
) {
412 /* disable checking for all banks */
415 serial_puts ("disable ECC.. ");
417 mtdcr (memcfga
, mem_ecccf
);
418 tmp
= mfdcr (memcfgd
);
419 tmp
&= 0xff0fffff; /* disable all banks */
420 mtdcr (memcfga
, mem_ecccf
);
421 /* set up SDRAM Controller with ECC enabled */
423 serial_puts ("setup SDRAM Controller.. ");
425 mtdcr (memcfgd
, tmp
);
426 mtdcr (memcfga
, mem_mcopt1
);
427 tmp
= (mfdcr (memcfgd
) & ~0xFFE00000) | 0x90800000;
428 mtdcr (memcfga
, mem_mcopt1
);
429 mtdcr (memcfgd
, tmp
);
432 serial_puts ("fill the memory..\n");
435 /* now, fill all the memory */
436 tmp
= ((4 * MEGA_BYTE
) << sdram_table
[i
].sz
);
437 p
= (unsigned long) 0;
438 while ((unsigned long) p
< tmp
) {
440 if (!((unsigned long) p
% 0x00800000)) /* every 8MByte */
446 serial_puts ("enable ECC\n");
449 mtdcr (memcfga
, mem_ecccf
);
450 tmp
= mfdcr (memcfgd
);
451 tmp
|= 0x00800000; /* enable bank 0 */
452 mtdcr (memcfgd
, tmp
);
457 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
458 mtdcr (memcfga
, mem_mcopt1
);
459 tmp
= (mfdcr (memcfgd
) & ~0xFFE00000) | 0x80C00000;
460 mtdcr (memcfga
, mem_mcopt1
);
461 mtdcr (memcfgd
, tmp
);
468 int board_early_init_f (void)
472 /*-------------------------------------------------------------------------+
473 | Interrupt controller setup for the PIP405 board.
474 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
475 | IRQ 16 405GP internally generated; active low; level sensitive
477 | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
478 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
479 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
480 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
481 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
482 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
483 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
484 | Note for MIP405 board:
485 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
486 | the Interrupt Controller in the South Bridge has caused the
487 | interrupt. The IC must be read to determine which device
488 | caused the interrupt.
490 +-------------------------------------------------------------------------*/
491 mtdcr (uicsr
, 0xFFFFFFFF); /* clear all ints */
492 mtdcr (uicer
, 0x00000000); /* disable all ints */
493 mtdcr (uiccr
, 0x00000000); /* set all to be non-critical (for now) */
494 mtdcr (uicpr
, 0xFFFFFF80); /* set int polarities */
495 mtdcr (uictr
, 0x10000000); /* set int trigger levels */
496 mtdcr (uicvcr
, 0x00000001); /* set vect base=0,INT0 highest priority */
497 mtdcr (uicsr
, 0xFFFFFFFF); /* clear all ints */
503 * Get some PLD Registers
506 unsigned short get_pld_parvers (void)
508 unsigned short result
;
511 rc
= in8 (PLD_PART_REG
);
512 result
= (unsigned short) rc
<< 8;
513 rc
= in8 (PLD_VERS_REG
);
519 void user_led0 (unsigned char on
)
522 out8 (PLD_COM_MODE_REG
, (in8 (PLD_COM_MODE_REG
) | 0x4));
524 out8 (PLD_COM_MODE_REG
, (in8 (PLD_COM_MODE_REG
) & 0xfb));
528 void ide_set_reset (int idereset
)
530 /* if reset = 1 IDE reset will be asserted */
532 out8 (PLD_COM_MODE_REG
, (in8 (PLD_COM_MODE_REG
) | 0x1));
535 out8 (PLD_COM_MODE_REG
, (in8 (PLD_COM_MODE_REG
) & 0xfe));
540 /* ------------------------------------------------------------------------- */
542 void get_pcbrev_var(unsigned char *pcbrev
, unsigned char *var
)
544 #if !defined(CONFIG_MIP405T)
545 unsigned char bc
,rc
,tmp
;
548 bc
= in8 (PLD_BOARD_CFG_REG
);
552 for (i
= 0; i
< 4; i
++) {
558 if(( (((bc
>>4) & 0xf)==0x2) /* Rev C PCB or */
559 || (((bc
>>4) & 0xf)==0x1)) /* Rev B PCB with */
560 && (rc
==0x1)) /* Population Option 1 is a -3 */
562 *pcbrev
=(bc
>> 4) & 0xf;
566 bc
= in8 (PLD_BOARD_CFG_REG
);
567 *pcbrev
=(bc
>> 4) & 0xf;
573 * Check Board Identity:
575 /* serial String: "MIP405_1000" OR "MIP405T_1000" */
576 #if !defined(CONFIG_MIP405T)
577 #define BOARD_NAME "MIP405"
579 #define BOARD_NAME "MIP405T"
582 int checkboard (void)
585 unsigned char bc
, var
;
587 backup_t
*b
= (backup_t
*) s
;
590 get_pcbrev_var(&bc
,&var
);
591 i
= getenv_r ("serial#", (char *)s
, 32);
592 if ((i
== 0) || strncmp ((char *)s
, BOARD_NAME
,sizeof(BOARD_NAME
))) {
593 get_backup_values (b
);
594 if (strncmp (b
->signature
, "MPL\0", 4) != 0) {
595 puts ("### No HW ID - assuming " BOARD_NAME
);
596 printf ("-%d Rev %c", var
, 'A' + bc
);
598 b
->serial_name
[sizeof(BOARD_NAME
)-1] = 0;
599 printf ("%s-%d Rev %c SN: %s", b
->serial_name
, var
,
600 'A' + bc
, &b
->serial_name
[sizeof(BOARD_NAME
)]);
603 s
[sizeof(BOARD_NAME
)-1] = 0;
604 printf ("%s-%d Rev %c SN: %s", s
, var
,'A' + bc
,
605 &s
[sizeof(BOARD_NAME
)]);
607 bc
= in8 (PLD_EXT_CONF_REG
);
608 printf (" Boot Config: 0x%x\n", bc
);
613 /* ------------------------------------------------------------------------- */
614 /* ------------------------------------------------------------------------- */
616 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
617 the necessary info for SDRAM controller configuration
619 /* ------------------------------------------------------------------------- */
620 /* ------------------------------------------------------------------------- */
621 static int test_dram (unsigned long ramsize
);
623 phys_size_t
initdram (int board_type
)
626 unsigned long bank_reg
[4], tmp
, bank_size
;
628 unsigned long TotalSize
;
631 /* since the DRAM controller is allready set up, calculate the size with the
633 mtdcr (memcfga
, mem_mb0cf
);
634 bank_reg
[0] = mfdcr (memcfgd
);
635 mtdcr (memcfga
, mem_mb1cf
);
636 bank_reg
[1] = mfdcr (memcfgd
);
637 mtdcr (memcfga
, mem_mb2cf
);
638 bank_reg
[2] = mfdcr (memcfgd
);
639 mtdcr (memcfga
, mem_mb3cf
);
640 bank_reg
[3] = mfdcr (memcfgd
);
642 for (i
= 0; i
< 4; i
++) {
643 if ((bank_reg
[i
] & 0x1) == 0x1) {
644 tmp
= (bank_reg
[i
] >> 17) & 0x7;
645 bank_size
= 4 << tmp
;
646 TotalSize
+= bank_size
;
650 mtdcr (memcfga
, mem_ecccf
);
651 tmp
= mfdcr (memcfgd
);
657 test_dram (TotalSize
* MEGA_BYTE
);
658 return (TotalSize
* MEGA_BYTE
);
661 /* ------------------------------------------------------------------------- */
664 static int test_dram (unsigned long ramsize
)
667 mem_test (0L, ramsize
, 1);
669 /* not yet implemented */
673 /* used to check if the time in RTC is valid */
674 static unsigned long start
;
675 static struct rtc_time tm
;
676 extern flash_info_t flash_info
[]; /* info for FLASH chips */
678 int misc_init_r (void)
680 /* adjust flash start and size as well as the offset */
681 gd
->bd
->bi_flashstart
=0-flash_info
[0].size
;
682 gd
->bd
->bi_flashsize
=flash_info
[0].size
-CONFIG_SYS_MONITOR_LEN
;
683 gd
->bd
->bi_flashoffset
=0;
685 /* check, if RTC is running */
688 /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
689 if (mfdcr(strap
) & PSR_ROM_LOC
)
690 mtspr(ccr0
, (mfspr(ccr0
) & ~0x80));
696 void print_mip405_rev (void)
698 unsigned char part
, vers
, pcbrev
, var
;
700 get_pcbrev_var(&pcbrev
,&var
);
701 part
= in8 (PLD_PART_REG
);
702 vers
= in8 (PLD_VERS_REG
);
703 printf ("Rev: " BOARD_NAME
"-%d Rev %c PLD %d Vers %d\n",
704 var
, pcbrev
+ 'A', part
& 0x7F, vers
);
710 * Returns 1 if keys pressed to start the power-on long-running tests
711 * Called from board_init_f().
713 int post_hotkeys_pressed(void)
715 return 0; /* No hotkeys supported */
719 extern void mem_test_reloc(void);
720 extern int mk_date (char *, struct rtc_time
*);
722 int last_stage_init (void)
725 struct rtc_time newtm
;
728 /* write correct LED configuration */
729 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
730 printf ("Error writing to the PHY\n");
732 /* since LED/CFG2 is not connected on the -2,
733 * write to correct capability information */
734 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
735 printf ("Error writing to the PHY\n");
740 /* check if RTC time is valid */
741 stop
=get_timer(start
);
742 while(stop
<1200) { /* we wait 1.2 sec to check if the RTC is running */
744 stop
=get_timer(start
);
747 if(tm
.tm_sec
==newtm
.tm_sec
) {
748 s
=getenv("defaultdate");
750 mk_date ("010112001970", &newtm
);
752 if(mk_date (s
, &newtm
)!=0) {
753 printf("RTC: Bad date format in defaultdate\n");
762 /***************************************************************************
763 * some helping routines
766 int overwrite_console (void)
768 return ((in8 (PLD_EXT_CONF_REG
) & 0x1)==0); /* return TRUE if console should be overwritten */
772 /************************************************************************
774 ************************************************************************/
775 void print_mip405_info (void)
777 unsigned char part
, vers
, cfg
, irq_reg
, com_mode
, ext
;
779 part
= in8 (PLD_PART_REG
);
780 vers
= in8 (PLD_VERS_REG
);
781 cfg
= in8 (PLD_BOARD_CFG_REG
);
782 irq_reg
= in8 (PLD_IRQ_REG
);
783 com_mode
= in8 (PLD_COM_MODE_REG
);
784 ext
= in8 (PLD_EXT_CONF_REG
);
786 printf ("PLD Part %d version %d\n", part
& 0x7F, vers
);
787 printf ("Board Revision %c\n", ((cfg
>> 4) & 0xf) + 'A');
788 printf ("Population Options %d %d %d %d\n", (cfg
) & 0x1,
789 (cfg
>> 1) & 0x1, (cfg
>> 2) & 0x1, (cfg
>> 3) & 0x1);
790 printf ("User LED %s\n", (com_mode
& 0x4) ? "on" : "off");
791 printf ("UART Clocks %d\n", (com_mode
>> 4) & 0x3);
792 #if !defined(CONFIG_MIP405T)
793 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
794 (ext
) & 0x1, (ext
>> 1) & 0x1, (ext
>> 2) & 0x1,
795 (ext
>> 3) & 0x1, (ext
>> 4) & 0x1, (ext
>> 5) & 0x1,
796 (ext
>> 6) & 0x1, (ext
>> 7) & 0x1);
797 printf ("SER1 uses handshakes %s\n",
798 (ext
& 0x80) ? "DTR/DSR" : "RTS/CTS");
800 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
801 (ext
) & 0x1, (ext
>> 1) & 0x1, (ext
>> 2) & 0x1,
802 (ext
>> 3) & 0x1, (ext
>> 4) & 0x1, (ext
>> 5) & 0x1,
803 (ext
>> 6) & 0x1,(ext
>> 7) & 0x1);
805 printf ("IDE Reset %s\n", (ext
& 0x01) ? "asserted" : "not asserted");
807 printf (" PIIX INTR: %s\n", (irq_reg
& 0x80) ? "inactive" : "active");
808 #if !defined(CONFIG_MIP405T)
809 printf (" UART0 IRQ: %s\n", (irq_reg
& 0x40) ? "inactive" : "active");
810 printf (" UART1 IRQ: %s\n", (irq_reg
& 0x20) ? "inactive" : "active");
812 printf (" PIIX SMI: %s\n", (irq_reg
& 0x10) ? "inactive" : "active");
813 printf (" PIIX INIT: %s\n", (irq_reg
& 0x8) ? "inactive" : "active");
814 printf (" PIIX NMI: %s\n", (irq_reg
& 0x4) ? "inactive" : "active");