]>
git.ipfire.org Git - people/ms/u-boot.git/blob - board/mpl/mip405/mip405.c
b87df01fec2648a4a65de7225254d6a421f66787
3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
30 * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
31 * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
32 * parameters from the datasheet are:
33 * Tclk = 7.5ns (CL = 2)
39 * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
40 * period is 10ns and the parameters needed for the Timing Register are:
41 * CASL = CL = 2 clock cycles
42 * PTA = Trp = 15ns / 10ns = 2 clock cycles
43 * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
44 * LDF = 2 clock cycles (but can be extended to meet board-level timing)
45 * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
46 * RCD = Trcd = 15ns / 10ns= 2 clock cycles
48 * The actual bit settings in the register would be:
57 * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
58 * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
59 * defined as Trc rather than Trfc.
60 * When using DIMM modules, most but not all of the required timing parameters can be read
61 * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
62 * are not available from the EEPROM
67 #include <asm/processor.h>
70 #include "../common/common_util.h"
71 #include <stdio_dev.h>
75 DECLARE_GLOBAL_DATA_PTR
;
78 #define ENABLE_ECC /* for ecc boards */
82 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
83 #ifndef __ldiv_t_defined
85 long int quot
; /* Quotient */
86 long int rem
; /* Remainder */
88 extern ldiv_t ldiv (long int __numer
, long int __denom
);
89 # define __ldiv_t_defined 1
93 #define PLD_PART_REG PER_PLD_ADDR + 0
94 #define PLD_VERS_REG PER_PLD_ADDR + 1
95 #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
96 #define PLD_IRQ_REG PER_PLD_ADDR + 3
97 #define PLD_COM_MODE_REG PER_PLD_ADDR + 4
98 #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
100 #define MEGA_BYTE (1024*1024)
103 unsigned char boardtype
; /* Board revision and Population Options */
104 unsigned char cal
; /* cas Latency (will be programmend as cal-1) */
105 unsigned char trp
; /* datain27 in clocks */
106 unsigned char trcd
; /* datain29 in clocks */
107 unsigned char tras
; /* datain30 in clocks */
108 unsigned char tctp
; /* tras - trcd in clocks */
109 unsigned char am
; /* Address Mod (will be programmed as am-1) */
110 unsigned char sz
; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
111 unsigned char ecc
; /* if true, ecc is enabled */
113 #if defined(CONFIG_MIP405T)
114 const sdram_t sdram_table
[] = {
115 { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
116 3, /* Case Latenty = 3 */
117 3, /* trp 20ns / 7.5 ns datain[27] */
118 3, /* trcd 20ns /7.5 ns (datain[29]) */
119 6, /* tras 44ns /7.5 ns (datain[30]) */
120 4, /* tcpt 44 - 20ns = 24ns */
121 2, /* Address Mode = 2 (12x9x4) */
122 3, /* size value (32MByte) */
123 0}, /* ECC disabled */
124 { 0xff, /* terminator */
134 const sdram_t sdram_table
[] = {
135 { 0x0f, /* Rev A, 128MByte -1 Board */
136 3, /* Case Latenty = 3 */
137 3, /* trp 20ns / 7.5 ns datain[27] */
138 3, /* trcd 20ns /7.5 ns (datain[29]) */
139 6, /* tras 44ns /7.5 ns (datain[30]) */
140 4, /* tcpt 44 - 20ns = 24ns */
141 3, /* Address Mode = 3 */
143 1}, /* ECC enabled */
144 { 0x07, /* Rev A, 64MByte -2 Board */
145 3, /* Case Latenty = 3 */
146 3, /* trp 20ns / 7.5 ns datain[27] */
147 3, /* trcd 20ns /7.5 ns (datain[29]) */
148 6, /* tras 44ns /7.5 ns (datain[30]) */
149 4, /* tcpt 44 - 20ns = 24ns */
150 2, /* Address Mode = 2 */
152 1}, /* ECC enabled */
153 { 0x03, /* Rev A, 128MByte -4 Board */
154 3, /* Case Latenty = 3 */
155 3, /* trp 20ns / 7.5 ns datain[27] */
156 3, /* trcd 20ns /7.5 ns (datain[29]) */
157 6, /* tras 44ns /7.5 ns (datain[30]) */
158 4, /* tcpt 44 - 20ns = 24ns */
159 3, /* Address Mode = 3 */
161 1}, /* ECC enabled */
162 { 0x1f, /* Rev B, 128MByte -3 Board */
163 3, /* Case Latenty = 3 */
164 3, /* trp 20ns / 7.5 ns datain[27] */
165 3, /* trcd 20ns /7.5 ns (datain[29]) */
166 6, /* tras 44ns /7.5 ns (datain[30]) */
167 4, /* tcpt 44 - 20ns = 24ns */
168 3, /* Address Mode = 3 */
170 1}, /* ECC enabled */
171 { 0x2f, /* Rev C, 128MByte -3 Board */
172 3, /* Case Latenty = 3 */
173 3, /* trp 20ns / 7.5 ns datain[27] */
174 3, /* trcd 20ns /7.5 ns (datain[29]) */
175 6, /* tras 44ns /7.5 ns (datain[30]) */
176 4, /* tcpt 44 - 20ns = 24ns */
177 3, /* Address Mode = 3 */
179 1}, /* ECC enabled */
180 { 0xff, /* terminator */
189 #endif /*CONFIG_MIP405T */
190 void SDRAM_err (const char *s
)
193 (void) get_clocks ();
199 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
204 unsigned char get_board_revcfg (void)
206 out8 (PER_BOARD_ADDR
, 0);
207 return (in8 (PER_BOARD_ADDR
));
213 void write_hex (unsigned char i
)
220 serial_putc (cc
+ 55);
222 serial_putc (cc
+ 48);
225 serial_putc (cc
+ 55);
227 serial_putc (cc
+ 48);
230 void write_4hex (unsigned long val
)
232 write_hex ((unsigned char) (val
>> 24));
233 write_hex ((unsigned char) (val
>> 16));
234 write_hex ((unsigned char) (val
>> 8));
235 write_hex ((unsigned char) val
);
241 int init_sdram (void)
243 unsigned long tmp
, baseaddr
;
245 unsigned char trp_clocks
,
250 unsigned char cal_val
;
252 unsigned long sdram_tim
, sdram_bank
;
254 /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/
255 (void) get_clocks ();
259 mtdcr (EBC0_CFGADDR
, PB7AP
);
260 mtdcr (EBC0_CFGDATA
, PLD_AP
);
261 mtdcr (EBC0_CFGADDR
, PB7CR
);
262 mtdcr (EBC0_CFGDATA
, PLD_CR
);
263 /* THIS IS OBSOLETE */
264 /* set up the board rev reg*/
265 mtdcr (EBC0_CFGADDR
, PB5AP
);
266 mtdcr (EBC0_CFGDATA
, BOARD_AP
);
267 mtdcr (EBC0_CFGADDR
, PB5CR
);
268 mtdcr (EBC0_CFGDATA
, BOARD_CR
);
270 /* get all informations from PLD */
271 serial_puts ("\nPLD Part 0x");
272 bc
= in8 (PLD_PART_REG
);
274 serial_puts ("\nPLD Vers 0x");
275 bc
= in8 (PLD_VERS_REG
);
277 serial_puts ("\nBoard Rev 0x");
278 bc
= in8 (PLD_BOARD_CFG_REG
);
283 bc
= in8 (PLD_PART_REG
);
284 #if defined(CONFIG_MIP405T)
286 SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
288 if((bc
& 0x80)==0x80)
289 SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
291 /* set-up the chipselect machine */
292 mtdcr (EBC0_CFGADDR
, PB0CR
); /* get cs0 config reg */
293 tmp
= mfdcr (EBC0_CFGDATA
);
294 if ((tmp
& 0x00002000) == 0) {
295 /* MPS Boot, set up the flash */
296 mtdcr (EBC0_CFGADDR
, PB1AP
);
297 mtdcr (EBC0_CFGDATA
, FLASH_AP
);
298 mtdcr (EBC0_CFGADDR
, PB1CR
);
299 mtdcr (EBC0_CFGDATA
, FLASH_CR
);
301 /* Flash boot, set up the MPS */
302 mtdcr (EBC0_CFGADDR
, PB1AP
);
303 mtdcr (EBC0_CFGDATA
, MPS_AP
);
304 mtdcr (EBC0_CFGADDR
, PB1CR
);
305 mtdcr (EBC0_CFGDATA
, MPS_CR
);
307 /* set up UART0 (CS2) and UART1 (CS3) */
308 mtdcr (EBC0_CFGADDR
, PB2AP
);
309 mtdcr (EBC0_CFGDATA
, UART0_AP
);
310 mtdcr (EBC0_CFGADDR
, PB2CR
);
311 mtdcr (EBC0_CFGDATA
, UART0_CR
);
312 mtdcr (EBC0_CFGADDR
, PB3AP
);
313 mtdcr (EBC0_CFGDATA
, UART1_AP
);
314 mtdcr (EBC0_CFGADDR
, PB3CR
);
315 mtdcr (EBC0_CFGDATA
, UART1_CR
);
316 bc
= in8 (PLD_BOARD_CFG_REG
);
318 serial_puts ("\nstart SDRAM Setup\n");
319 serial_puts ("\nBoard Rev: ");
324 baseaddr
= CONFIG_SYS_SDRAM_BASE
;
325 while (sdram_table
[i
].sz
!= 0xff) {
326 if (sdram_table
[i
].boardtype
== bc
)
330 if (sdram_table
[i
].boardtype
!= bc
)
331 SDRAM_err ("No SDRAM table found for this board!!!\n");
333 serial_puts (" found table ");
337 /* since the ECC initialisation needs some time,
338 * we show that we're alive
340 if (sdram_table
[i
].ecc
)
341 serial_puts ("\nInitializing SDRAM, Please stand by");
342 cal_val
= sdram_table
[i
].cal
- 1; /* Cas Latency */
343 trp_clocks
= sdram_table
[i
].trp
; /* 20ns / 7.5 ns datain[27] */
344 trcd_clocks
= sdram_table
[i
].trcd
; /* 20ns /7.5 ns (datain[29]) */
345 tras_clocks
= sdram_table
[i
].tras
; /* 44ns /7.5 ns (datain[30]) */
346 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
347 tctp_clocks
= sdram_table
[i
].tctp
; /* 44 - 20ns = 24ns */
348 /* trc_clocks is sum of trp_clocks + tras_clocks */
349 trc_clocks
= trp_clocks
+ tras_clocks
;
350 /* get SDRAM timing register */
351 mtdcr (SDRAM0_CFGADDR
, mem_sdtr1
);
352 sdram_tim
= mfdcr (SDRAM0_CFGDATA
) & ~0x018FC01F;
353 /* insert CASL value */
354 sdram_tim
|= ((unsigned long) (cal_val
)) << 23;
355 /* insert PTA value */
356 sdram_tim
|= ((unsigned long) (trp_clocks
- 1)) << 18;
357 /* insert CTP value */
359 ((unsigned long) (trc_clocks
- trp_clocks
-
361 /* insert LDF (always 01) */
362 sdram_tim
|= ((unsigned long) 0x01) << 14;
363 /* insert RFTA value */
364 sdram_tim
|= ((unsigned long) (trc_clocks
- 4)) << 2;
365 /* insert RCD value */
366 sdram_tim
|= ((unsigned long) (trcd_clocks
- 1)) << 0;
368 tmp
= ((unsigned long) (sdram_table
[i
].am
- 1) << 13); /* AM = 3 */
369 /* insert SZ value; */
370 tmp
|= ((unsigned long) sdram_table
[i
].sz
<< 17);
371 /* get SDRAM bank 0 register */
372 mtdcr (SDRAM0_CFGADDR
, mem_mb0cf
);
373 sdram_bank
= mfdcr (SDRAM0_CFGDATA
) & ~0xFFCEE001;
374 sdram_bank
|= (baseaddr
| tmp
| 0x01);
377 serial_puts ("sdtr: ");
378 write_4hex (sdram_tim
);
382 /* write SDRAM timing register */
383 mtdcr (SDRAM0_CFGADDR
, mem_sdtr1
);
384 mtdcr (SDRAM0_CFGDATA
, sdram_tim
);
387 serial_puts ("mb0cf: ");
388 write_4hex (sdram_bank
);
392 /* write SDRAM bank 0 register */
393 mtdcr (SDRAM0_CFGADDR
, mem_mb0cf
);
394 mtdcr (SDRAM0_CFGDATA
, sdram_bank
);
396 if (get_bus_freq (tmp
) > 110000000) { /* > 110MHz */
397 /* get SDRAM refresh interval register */
398 mtdcr (SDRAM0_CFGADDR
, mem_rtr
);
399 tmp
= mfdcr (SDRAM0_CFGDATA
) & ~0x3FF80000;
402 /* get SDRAM refresh interval register */
403 mtdcr (SDRAM0_CFGADDR
, mem_rtr
);
404 tmp
= mfdcr (SDRAM0_CFGDATA
) & ~0x3FF80000;
407 /* write SDRAM refresh interval register */
408 mtdcr (SDRAM0_CFGADDR
, mem_rtr
);
409 mtdcr (SDRAM0_CFGDATA
, tmp
);
410 /* enable ECC if used */
411 #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
412 if (sdram_table
[i
].ecc
) {
413 /* disable checking for all banks */
416 serial_puts ("disable ECC.. ");
418 mtdcr (SDRAM0_CFGADDR
, mem_ecccf
);
419 tmp
= mfdcr (SDRAM0_CFGDATA
);
420 tmp
&= 0xff0fffff; /* disable all banks */
421 mtdcr (SDRAM0_CFGADDR
, mem_ecccf
);
422 /* set up SDRAM Controller with ECC enabled */
424 serial_puts ("setup SDRAM Controller.. ");
426 mtdcr (SDRAM0_CFGDATA
, tmp
);
427 mtdcr (SDRAM0_CFGADDR
, mem_mcopt1
);
428 tmp
= (mfdcr (SDRAM0_CFGDATA
) & ~0xFFE00000) | 0x90800000;
429 mtdcr (SDRAM0_CFGADDR
, mem_mcopt1
);
430 mtdcr (SDRAM0_CFGDATA
, tmp
);
433 serial_puts ("fill the memory..\n");
436 /* now, fill all the memory */
437 tmp
= ((4 * MEGA_BYTE
) << sdram_table
[i
].sz
);
438 p
= (unsigned long) 0;
439 while ((unsigned long) p
< tmp
) {
441 if (!((unsigned long) p
% 0x00800000)) /* every 8MByte */
447 serial_puts ("enable ECC\n");
450 mtdcr (SDRAM0_CFGADDR
, mem_ecccf
);
451 tmp
= mfdcr (SDRAM0_CFGDATA
);
452 tmp
|= 0x00800000; /* enable bank 0 */
453 mtdcr (SDRAM0_CFGDATA
, tmp
);
458 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
459 mtdcr (SDRAM0_CFGADDR
, mem_mcopt1
);
460 tmp
= (mfdcr (SDRAM0_CFGDATA
) & ~0xFFE00000) | 0x80C00000;
461 mtdcr (SDRAM0_CFGADDR
, mem_mcopt1
);
462 mtdcr (SDRAM0_CFGDATA
, tmp
);
469 int board_early_init_f (void)
473 /*-------------------------------------------------------------------------+
474 | Interrupt controller setup for the PIP405 board.
475 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
476 | IRQ 16 405GP internally generated; active low; level sensitive
478 | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
479 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
480 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
481 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
482 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
483 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
484 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
485 | Note for MIP405 board:
486 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
487 | the Interrupt Controller in the South Bridge has caused the
488 | interrupt. The IC must be read to determine which device
489 | caused the interrupt.
491 +-------------------------------------------------------------------------*/
492 mtdcr (UIC0SR
, 0xFFFFFFFF); /* clear all ints */
493 mtdcr (UIC0ER
, 0x00000000); /* disable all ints */
494 mtdcr (UIC0CR
, 0x00000000); /* set all to be non-critical (for now) */
495 mtdcr (UIC0PR
, 0xFFFFFF80); /* set int polarities */
496 mtdcr (UIC0TR
, 0x10000000); /* set int trigger levels */
497 mtdcr (UIC0VCR
, 0x00000001); /* set vect base=0,INT0 highest priority */
498 mtdcr (UIC0SR
, 0xFFFFFFFF); /* clear all ints */
504 * Get some PLD Registers
507 unsigned short get_pld_parvers (void)
509 unsigned short result
;
512 rc
= in8 (PLD_PART_REG
);
513 result
= (unsigned short) rc
<< 8;
514 rc
= in8 (PLD_VERS_REG
);
520 void user_led0 (unsigned char on
)
523 out8 (PLD_COM_MODE_REG
, (in8 (PLD_COM_MODE_REG
) | 0x4));
525 out8 (PLD_COM_MODE_REG
, (in8 (PLD_COM_MODE_REG
) & 0xfb));
529 void ide_set_reset (int idereset
)
531 /* if reset = 1 IDE reset will be asserted */
533 out8 (PLD_COM_MODE_REG
, (in8 (PLD_COM_MODE_REG
) | 0x1));
536 out8 (PLD_COM_MODE_REG
, (in8 (PLD_COM_MODE_REG
) & 0xfe));
541 /* ------------------------------------------------------------------------- */
543 void get_pcbrev_var(unsigned char *pcbrev
, unsigned char *var
)
545 #if !defined(CONFIG_MIP405T)
546 unsigned char bc
,rc
,tmp
;
549 bc
= in8 (PLD_BOARD_CFG_REG
);
553 for (i
= 0; i
< 4; i
++) {
559 if(( (((bc
>>4) & 0xf)==0x2) /* Rev C PCB or */
560 || (((bc
>>4) & 0xf)==0x1)) /* Rev B PCB with */
561 && (rc
==0x1)) /* Population Option 1 is a -3 */
563 *pcbrev
=(bc
>> 4) & 0xf;
567 bc
= in8 (PLD_BOARD_CFG_REG
);
568 *pcbrev
=(bc
>> 4) & 0xf;
574 * Check Board Identity:
576 /* serial String: "MIP405_1000" OR "MIP405T_1000" */
577 #if !defined(CONFIG_MIP405T)
578 #define BOARD_NAME "MIP405"
580 #define BOARD_NAME "MIP405T"
583 int checkboard (void)
586 unsigned char bc
, var
;
588 backup_t
*b
= (backup_t
*) s
;
591 get_pcbrev_var(&bc
,&var
);
592 i
= getenv_r ("serial#", (char *)s
, 32);
593 if ((i
== 0) || strncmp ((char *)s
, BOARD_NAME
,sizeof(BOARD_NAME
))) {
594 get_backup_values (b
);
595 if (strncmp (b
->signature
, "MPL\0", 4) != 0) {
596 puts ("### No HW ID - assuming " BOARD_NAME
);
597 printf ("-%d Rev %c", var
, 'A' + bc
);
599 b
->serial_name
[sizeof(BOARD_NAME
)-1] = 0;
600 printf ("%s-%d Rev %c SN: %s", b
->serial_name
, var
,
601 'A' + bc
, &b
->serial_name
[sizeof(BOARD_NAME
)]);
604 s
[sizeof(BOARD_NAME
)-1] = 0;
605 printf ("%s-%d Rev %c SN: %s", s
, var
,'A' + bc
,
606 &s
[sizeof(BOARD_NAME
)]);
608 bc
= in8 (PLD_EXT_CONF_REG
);
609 printf (" Boot Config: 0x%x\n", bc
);
614 /* ------------------------------------------------------------------------- */
615 /* ------------------------------------------------------------------------- */
617 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
618 the necessary info for SDRAM controller configuration
620 /* ------------------------------------------------------------------------- */
621 /* ------------------------------------------------------------------------- */
622 static int test_dram (unsigned long ramsize
);
624 phys_size_t
initdram (int board_type
)
627 unsigned long bank_reg
[4], tmp
, bank_size
;
629 unsigned long TotalSize
;
632 /* since the DRAM controller is allready set up, calculate the size with the
634 mtdcr (SDRAM0_CFGADDR
, mem_mb0cf
);
635 bank_reg
[0] = mfdcr (SDRAM0_CFGDATA
);
636 mtdcr (SDRAM0_CFGADDR
, mem_mb1cf
);
637 bank_reg
[1] = mfdcr (SDRAM0_CFGDATA
);
638 mtdcr (SDRAM0_CFGADDR
, mem_mb2cf
);
639 bank_reg
[2] = mfdcr (SDRAM0_CFGDATA
);
640 mtdcr (SDRAM0_CFGADDR
, mem_mb3cf
);
641 bank_reg
[3] = mfdcr (SDRAM0_CFGDATA
);
643 for (i
= 0; i
< 4; i
++) {
644 if ((bank_reg
[i
] & 0x1) == 0x1) {
645 tmp
= (bank_reg
[i
] >> 17) & 0x7;
646 bank_size
= 4 << tmp
;
647 TotalSize
+= bank_size
;
651 mtdcr (SDRAM0_CFGADDR
, mem_ecccf
);
652 tmp
= mfdcr (SDRAM0_CFGDATA
);
658 test_dram (TotalSize
* MEGA_BYTE
);
659 return (TotalSize
* MEGA_BYTE
);
662 /* ------------------------------------------------------------------------- */
665 static int test_dram (unsigned long ramsize
)
668 mem_test (0L, ramsize
, 1);
670 /* not yet implemented */
674 /* used to check if the time in RTC is valid */
675 static unsigned long start
;
676 static struct rtc_time tm
;
677 extern flash_info_t flash_info
[]; /* info for FLASH chips */
679 int misc_init_r (void)
681 /* adjust flash start and size as well as the offset */
682 gd
->bd
->bi_flashstart
=0-flash_info
[0].size
;
683 gd
->bd
->bi_flashsize
=flash_info
[0].size
-CONFIG_SYS_MONITOR_LEN
;
684 gd
->bd
->bi_flashoffset
=0;
686 /* check, if RTC is running */
689 /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
690 if (mfdcr(CPC0_PSR
) & PSR_ROM_LOC
)
691 mtspr(SPRN_CCR0
, (mfspr(SPRN_CCR0
) & ~0x80));
697 void print_mip405_rev (void)
699 unsigned char part
, vers
, pcbrev
, var
;
701 get_pcbrev_var(&pcbrev
,&var
);
702 part
= in8 (PLD_PART_REG
);
703 vers
= in8 (PLD_VERS_REG
);
704 printf ("Rev: " BOARD_NAME
"-%d Rev %c PLD %d Vers %d\n",
705 var
, pcbrev
+ 'A', part
& 0x7F, vers
);
711 * Returns 1 if keys pressed to start the power-on long-running tests
712 * Called from board_init_f().
714 int post_hotkeys_pressed(void)
716 return 0; /* No hotkeys supported */
720 extern void mem_test_reloc(void);
721 extern int mk_date (char *, struct rtc_time
*);
723 int last_stage_init (void)
726 struct rtc_time newtm
;
729 /* write correct LED configuration */
730 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
731 printf ("Error writing to the PHY\n");
733 /* since LED/CFG2 is not connected on the -2,
734 * write to correct capability information */
735 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
736 printf ("Error writing to the PHY\n");
739 stdio_print_current_devices ();
741 /* check if RTC time is valid */
742 stop
=get_timer(start
);
743 while(stop
<1200) { /* we wait 1.2 sec to check if the RTC is running */
745 stop
=get_timer(start
);
748 if(tm
.tm_sec
==newtm
.tm_sec
) {
749 s
=getenv("defaultdate");
751 mk_date ("010112001970", &newtm
);
753 if(mk_date (s
, &newtm
)!=0) {
754 printf("RTC: Bad date format in defaultdate\n");
763 /***************************************************************************
764 * some helping routines
767 int overwrite_console (void)
769 return ((in8 (PLD_EXT_CONF_REG
) & 0x1)==0); /* return TRUE if console should be overwritten */
773 /************************************************************************
775 ************************************************************************/
776 void print_mip405_info (void)
778 unsigned char part
, vers
, cfg
, irq_reg
, com_mode
, ext
;
780 part
= in8 (PLD_PART_REG
);
781 vers
= in8 (PLD_VERS_REG
);
782 cfg
= in8 (PLD_BOARD_CFG_REG
);
783 irq_reg
= in8 (PLD_IRQ_REG
);
784 com_mode
= in8 (PLD_COM_MODE_REG
);
785 ext
= in8 (PLD_EXT_CONF_REG
);
787 printf ("PLD Part %d version %d\n", part
& 0x7F, vers
);
788 printf ("Board Revision %c\n", ((cfg
>> 4) & 0xf) + 'A');
789 printf ("Population Options %d %d %d %d\n", (cfg
) & 0x1,
790 (cfg
>> 1) & 0x1, (cfg
>> 2) & 0x1, (cfg
>> 3) & 0x1);
791 printf ("User LED %s\n", (com_mode
& 0x4) ? "on" : "off");
792 printf ("UART Clocks %d\n", (com_mode
>> 4) & 0x3);
793 #if !defined(CONFIG_MIP405T)
794 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
795 (ext
) & 0x1, (ext
>> 1) & 0x1, (ext
>> 2) & 0x1,
796 (ext
>> 3) & 0x1, (ext
>> 4) & 0x1, (ext
>> 5) & 0x1,
797 (ext
>> 6) & 0x1, (ext
>> 7) & 0x1);
798 printf ("SER1 uses handshakes %s\n",
799 (ext
& 0x80) ? "DTR/DSR" : "RTS/CTS");
801 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
802 (ext
) & 0x1, (ext
>> 1) & 0x1, (ext
>> 2) & 0x1,
803 (ext
>> 3) & 0x1, (ext
>> 4) & 0x1, (ext
>> 5) & 0x1,
804 (ext
>> 6) & 0x1,(ext
>> 7) & 0x1);
806 printf ("IDE Reset %s\n", (ext
& 0x01) ? "asserted" : "not asserted");
808 printf (" PIIX INTR: %s\n", (irq_reg
& 0x80) ? "inactive" : "active");
809 #if !defined(CONFIG_MIP405T)
810 printf (" UART0 IRQ: %s\n", (irq_reg
& 0x40) ? "inactive" : "active");
811 printf (" UART1 IRQ: %s\n", (irq_reg
& 0x20) ? "inactive" : "active");
813 printf (" PIIX SMI: %s\n", (irq_reg
& 0x10) ? "inactive" : "active");
814 printf (" PIIX INIT: %s\n", (irq_reg
& 0x8) ? "inactive" : "active");
815 printf (" PIIX NMI: %s\n", (irq_reg
& 0x4) ? "inactive" : "active");