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git.ipfire.org Git - people/ms/u-boot.git/blob - board/mpl/pati/pati.c
3 * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
5 * Denis Peter, d.peter@mpl.ch
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /***********************************************************************************
26 * Bits for the SDRAM controller
27 * -----------------------------
29 * CAL: CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on
30 * the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM
31 * controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3).
32 * RCD: RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default)
33 * tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns.
34 * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns.
35 * If set to 1 tWR must be equal or less 50ns.
36 * RP: Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less
37 * 25ns. If set to 1 tRP must be equal or less 50ns.
38 * RC: Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal
39 * or less 75ns. If set to 1 tRC must be equal or less 100ns.
40 * LMR: Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM
41 * is the Load Mode Register Command.
42 * IIP: Init in progress. Set to 1 for starting the init sequence
43 * (Precharge All). As long this bit is set, the Precharge All is still in progress.
44 * After command has completed, wait at least for 8 refresh (200usec) before proceed.
45 **********************************************************************************/
55 #if defined(__APPLE__)
56 /* Leading underscore on symbols */
58 #else /* No leading character on symbols */
64 * Macros to generate global absolutes.
66 #define GEN_SYMNAME(str) SYM_CHAR #str
67 #define GEN_VALUE(str) #str
68 #define GEN_ABS(name, value) \
69 asm (".globl " GEN_SYMNAME(name)); \
70 asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
73 /************************************************************************
74 * Early debug routines
76 void write_hex (unsigned char i
)
83 serial_putc (cc
+ 55);
85 serial_putc (cc
+ 48);
88 serial_putc (cc
+ 55);
90 serial_putc (cc
+ 48);
93 #if defined(SDRAM_DEBUG)
95 void write_4hex (unsigned long val
)
97 write_hex ((unsigned char) (val
>> 24));
98 write_hex ((unsigned char) (val
>> 16));
99 write_hex ((unsigned char) (val
>> 8));
100 write_hex ((unsigned char) val
);
105 unsigned long in32(unsigned long addr
)
107 unsigned long *p
=(unsigned long *)addr
;
111 void out32(unsigned long addr
,unsigned long data
)
113 unsigned long *p
=(unsigned long *)addr
;
118 unsigned short boardtype
; /* Board revision and Population Options */
119 unsigned char cal
; /* cas Latency 0:CAL=2 1:CAL=3 */
120 unsigned char rcd
; /* ras to cas delay 0:<25ns 1:<50ns*/
121 unsigned char wrec
; /* write recovery 0:<25ns 1:<50ns */
122 unsigned char pr
; /* Precharge Command Time 0:<25ns 1:<50ns */
123 unsigned char rc
; /* Auto Refresh to Active Time 0:<75ns 1:<100ns */
124 unsigned char sz
; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
127 const sdram_t sdram_table
[] = {
128 { 0x0000, /* PATI Rev A, 16MByte -1 Board */
129 1, /* Case Latenty = 3 */
130 0, /* ras to cas delay 0 (20ns) */
131 0, /* write recovery 0:<25ns 1:<50ns*/
132 0, /* Precharge Command Time 0 (20ns) */
133 0, /* Auto Refresh to Active Time 0 (68) */
134 2 /* log binary => Size 2 = 16MByte, 1=8 */
136 { 0xffff, /* terminator */
146 extern int mem_test (unsigned long start
, unsigned long ramsize
, int quiet
);
147 extern void mem_test_reloc(void);
152 phys_size_t
initdram(int board_type
)
154 unsigned char board_rev
;
159 #if defined(SDRAM_DEBUG)
160 reg
=in32(PLD_CONFIG_BASE
+PLD_PART_ID
);
161 puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg
));
162 puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg
));
163 puts("\nSDRAM part 0x"); write_4hex(SDRAM_PART(reg
));
164 puts(" Vers 0x"); write_4hex(SDRAM_ID(reg
));
165 reg
=in32(PLD_CONFIG_BASE
+PLD_BOARD_TIMING
);
166 puts("\nBoard rev. 0x"); write_4hex(SYSCNTR_BREV(reg
));
169 reg
=in32(PLD_CONFIG_BASE
+PLD_BOARD_TIMING
);
170 board_rev
=(unsigned char)(SYSCNTR_BREV(reg
));
173 if(sdram_table
[i
].boardtype
==0xffff) {
174 puts("ERROR, found no table for Board 0x");
175 write_hex(board_rev
);
178 if(sdram_table
[i
].boardtype
==(unsigned char)board_rev
)
182 /* Set CAL, RCD, WREQ, PR and RC Bits */
183 #if defined(SDRAM_DEBUG)
184 puts("Set CAL, RCD, WREQ, PR and RC Bits\n");
187 reg
&= ~(SET_REG_BIT(1,SDRAM_CAL
) | SET_REG_BIT(1,SDRAM_RCD
) | SET_REG_BIT(1,SDRAM_WREQ
) |
188 SET_REG_BIT(1,SDRAM_PR
) | SET_REG_BIT(1,SDRAM_RC
) | SET_REG_BIT(1,SDRAM_LMR
) |
189 SET_REG_BIT(1,SDRAM_IIP
) | SET_REG_BIT(1,SDRAM_RES0
));
191 reg
|= (SET_REG_BIT(sdram_table
[i
].cal
,SDRAM_CAL
) |
192 SET_REG_BIT(sdram_table
[i
].rcd
,SDRAM_RCD
) |
193 SET_REG_BIT(sdram_table
[i
].wrec
,SDRAM_WREQ
) |
194 SET_REG_BIT(sdram_table
[i
].pr
,SDRAM_PR
) |
195 SET_REG_BIT(sdram_table
[i
].rc
,SDRAM_RC
));
197 out32(PLD_CONFIG_BASE
+PLD_BOARD_TIMING
,reg
);
199 #if defined(SDRAM_DEBUG)
200 puts("step 2 set IIP\n");
203 reg
|= SET_REG_BIT(1,SDRAM_IIP
);
205 while (timeout
!=0xffff) {
206 __asm__
volatile("eieio");
207 reg
=in32(PLD_CONFIG_BASE
+PLD_BOARD_TIMING
);
208 if((reg
& SET_REG_BIT(1,SDRAM_IIP
))==0)
213 /* wait for at least 8 refresh */
216 reg
|= SET_REG_BIT(1,SDRAM_LMR
);
217 out32(PLD_CONFIG_BASE
+PLD_BOARD_TIMING
,reg
);
218 __asm__
volatile("eieio");
219 lmr
=0x00000002; /* sequential burst 4 data */
220 if(sdram_table
[i
].cal
==1)
221 lmr
|=0x00000030; /* cal = 3 */
223 lmr
|=0000000020; /* cal = 2 */
224 /* rest standard operation programmed write burst length */
225 /* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */
227 in32(CONFIG_SYS_SDRAM_BASE
+ lmr
);
228 /* ok, we're done, return SDRAM size */
229 return ((0x400000 << sdram_table
[i
].sz
)); /* log2 value of 4MByte */
233 void set_flash_vpp(int ext_vpp
, int ext_wp
, int int_vpp
)
236 reg
=in32(PLD_CONF_REG2
+PLD_CONFIG_BASE
);
237 reg
&= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP
) |
238 SET_REG_BIT(1,SYSCNTR_FL_VPP
) |
239 SET_REG_BIT(1,SYSCNTR_FL_WP
));
241 reg
|= (SET_REG_BIT(int_vpp
,SYSCNTR_CPU_VPP
) |
242 SET_REG_BIT(ext_vpp
,SYSCNTR_FL_VPP
) |
243 SET_REG_BIT(ext_wp
,SYSCNTR_FL_WP
));
244 out32(PLD_CONF_REG2
+PLD_CONFIG_BASE
,reg
);
249 void show_pld_regs(void)
251 unsigned long reg
,reg1
;
252 reg
=in32(PLD_CONFIG_BASE
+PLD_PART_ID
);
253 printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg
),SYSCNTR_ID(reg
));
254 printf("SDRAM part %ld, Vers %ld\n",SDRAM_PART(reg
),SDRAM_ID(reg
));
255 reg
=in32(PLD_CONFIG_BASE
+PLD_BOARD_TIMING
);
256 printf("Board rev. %c\n",(char) (SYSCNTR_BREV(reg
)+'A'));
257 printf("Waitstates %ld\n",GET_SYSCNTR_FLWAIT(reg
));
258 printf("SDRAM: CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n RC=%ld LMR=%ld IIP=%ld\n",
259 GET_REG_BIT(reg
,SDRAM_CAL
),GET_REG_BIT(reg
,SDRAM_RCD
),
260 GET_REG_BIT(reg
,SDRAM_WREQ
),GET_REG_BIT(reg
,SDRAM_PR
),
261 GET_REG_BIT(reg
,SDRAM_RC
),GET_REG_BIT(reg
,SDRAM_LMR
),
262 GET_REG_BIT(reg
,SDRAM_IIP
));
263 reg
=in32(PLD_CONFIG_BASE
+PLD_CONF_REG1
);
264 reg1
=in32(PLD_CONFIG_BASE
+PLD_CONF_REG2
);
265 printf("HW Config: FLAG=%ld IP=%ld index=%ld PRPM=%ld\n ICW=%ld ISB=%ld BDIS=%ld PCIM=%ld\n",
266 GET_REG_BIT(reg
,SYSCNTR_FLAG
),GET_REG_BIT(reg
,SYSCNTR_IP
),
267 GET_SYSCNTR_BOOTIND(reg
),GET_REG_BIT(reg
,SYSCNTR_PRM
),
268 GET_REG_BIT(reg
,SYSCNTR_ICW
),GET_SYSCNTR_ISB(reg
),
269 GET_REG_BIT(reg1
,SYSCNTR_BDIS
),GET_REG_BIT(reg1
,SYSCNTR_PCIM
));
270 printf("Switches: MUX=%ld PCI_DIS=%ld Boot_EN=%ld Config=%ld\n",GET_SDRAM_MUX(reg
),
271 GET_REG_BIT(reg
,SDRAM_PDIS
),GET_REG_BIT(reg1
,SYSCNTR_BOOTEN
),
272 GET_SYSCNTR_CFG(reg1
));
273 printf("Misc: RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n",
274 GET_REG_BIT(reg
,SDRAM_RIP
),GET_REG_BIT(reg1
,SYSCNTR_CPU_VPP
),
275 GET_REG_BIT(reg1
,SYSCNTR_FL_VPP
),GET_REG_BIT(reg1
,SYSCNTR_FL_WP
));
279 /****************************************************************
283 * GPIO7 is Interrupt PLX (Output)
285 * GPIO2 is PLX USERi (Output)
286 * GPIO1 is PLX Interrupt (Input)
287 ****************************************************************/
290 volatile immap_t
* immr
= (immap_t
*) CONFIG_SYS_IMMR
;
291 volatile sysconf5xx_t
*sysconf
= &immr
->im_siu_conf
;
293 reg
=sysconf
->sc_sgpiocr
; /* Data direction register */
295 reg
|= 0x27000000; /* set outpupts */
296 sysconf
->sc_sgpiocr
=reg
; /* Data direction register */
297 reg
=sysconf
->sc_sgpiodt2
; /* Data register */
298 /* set output to 0 */
300 /* set IRQ and USERi to 1 */
302 sysconf
->sc_sgpiodt2
=reg
; /* Data register */
305 void user_led0(int led_on
)
307 volatile immap_t
* immr
= (immap_t
*) CONFIG_SYS_IMMR
;
308 volatile sysconf5xx_t
*sysconf
= &immr
->im_siu_conf
;
310 reg
=sysconf
->sc_sgpiodt2
; /* Data register */
311 if(led_on
) /* set output to 1 */
315 sysconf
->sc_sgpiodt2
=reg
; /* Data register */
318 void user_led1(int led_on
)
320 volatile immap_t
* immr
= (immap_t
*) CONFIG_SYS_IMMR
;
321 volatile sysconf5xx_t
*sysconf
= &immr
->im_siu_conf
;
323 reg
=sysconf
->sc_sgpiodt2
; /* Data register */
324 if(led_on
) /* set output to 1 */
328 sysconf
->sc_sgpiodt2
=reg
; /* Data register */
332 /****************************************************************
334 ****************************************************************/
335 int last_stage_init (void)
342 /****************************************************************
344 ****************************************************************/
346 #define BOARD_NAME "PATI"
348 int checkboard (void)
356 reg
=in32(PLD_CONFIG_BASE
+PLD_BOARD_TIMING
);
357 rev
=(char)(SYSCNTR_BREV(reg
)+'A');
358 i
= getenv_r ("serial#", s
, 32);
360 puts ("### No HW ID - assuming " BOARD_NAME
);
361 printf(" Rev. %c\n",rev
);
364 s
[sizeof(BOARD_NAME
)-1] = 0;
365 printf ("%s-1 Rev %c SN: %s\n", s
,rev
,
366 &s
[sizeof(BOARD_NAME
)]);
368 set_flash_vpp(1,0,0); /* set Flash VPP */
373 #ifdef CONFIG_SYS_PCI_CON_DEVICE
374 /************************************************************************
379 * PCI Host sends message ALIVE, Local acknowledges with ALIVE
381 * PCI_CON console over PCI:
382 * -------------------------
384 * - uses PCI9056_LOC_TO_PCI_DBELL register to signal that
385 * data is avaible (PCIMSG_CONN)
386 * - uses PCI9056_MAILBOX1 to send data
387 * - uses PCI9056_MAILBOX0 to receive data
389 * - uses PCI9056_PCI_TO_LOC_DBELL register to signal that
390 * data is avaible (PCIMSG_CONN)
391 * - uses PCI9056_MAILBOX0 to send data
392 * - uses PCI9056_MAILBOX1 to receive data
396 * - check if PCICON_TRANSMIT_REG is empty
397 * - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG
398 * - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data
401 * - get an interrupt via the PCICON_ACK_REG register message
403 * - write the data from the PCICON_RECEIVE_REG into the receive
404 * buffer and if the receive buffer is not full, clear the
405 * PCICON_RECEIVE_REG (this allows the counterpart to write more data)
406 * - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG
408 * The PCICON_RECEIVE_REG must be cleared by the routine which reads
409 * the receive buffer if the buffer is not full any more
416 #define PCI_CON_PRINTF(fmt,args...) serial_printf (fmt ,##args)
418 #define PCI_CON_PRINTF(fmt,args...)
422 /*********************************************************
423 * we work only with a receive buffer on eiter side.
424 * Transmit buffer is free, if mailbox is cleared.
425 * Transmit character is or'ed with 0x80000000
426 * PATI receive register MAILBOX0
427 * PATI transmit register MAILBOX1
428 *********************************************************/
429 #define PCICON_RECEIVE_REG PCI9056_MAILBOX0
430 #define PCICON_TRANSMIT_REG PCI9056_MAILBOX1
431 #define PCICON_DBELL_REG PCI9056_LOC_TO_PCI_DBELL
432 #define PCICON_ACK_REG PCI9056_PCI_TO_LOC_DBELL
435 #define PCIMSG_ALIVE 0x1
436 #define PCIMSG_CONN 0x2
437 #define PCIMSG_DISC 0x3
438 #define PCIMSG_CON_DATA 0x5
441 #define PCICON_GET_REG(x) (in32(x + PCI_CONFIG_BASE))
442 #define PCICON_SET_REG(x,y) (out32(x + PCI_CONFIG_BASE,y))
443 #define PCICON_TX_FLAG 0x80000000
446 #define REC_BUFFER_SIZE 0x100
447 int recbuf
[REC_BUFFER_SIZE
];
448 static int r_ptr
= 0;
450 device_t pci_con_dev
;
454 void pci_con_put_it(const char c
)
456 /* Test for completition */
459 reg
=PCICON_GET_REG(PCICON_TRANSMIT_REG
);
461 reg
=PCICON_TX_FLAG
+ c
;
462 PCICON_SET_REG(PCICON_TRANSMIT_REG
,reg
);
463 PCICON_SET_REG(PCICON_DBELL_REG
,PCIMSG_CON_DATA
);
466 void pci_con_putc(const char c
)
470 pci_con_put_it('\r');
474 int pci_con_getc(void)
478 while(r_ptr
==(volatile int)w_ptr
);
480 if(r_ptr
==REC_BUFFER_SIZE
)
483 diff
=r_ptr
+REC_BUFFER_SIZE
-w_ptr
;
486 if((diff
<(REC_BUFFER_SIZE
-4)) && buff_full
) {
489 PCICON_SET_REG(PCICON_RECEIVE_REG
,0L);
494 int pci_con_tstc(void)
496 if(r_ptr
==(volatile int)w_ptr
)
501 void pci_con_puts (const char *s
)
509 void pci_con_init (void)
513 PCICON_SET_REG(PCICON_RECEIVE_REG
,0L);
517 /*******************************************
519 ******************************************/
520 int pci_dorbell_irq(void)
522 unsigned long reg
,data
;
524 reg
=PCICON_GET_REG(PCI9056_INT_CTRL_STAT
);
525 PCI_CON_PRINTF(" PCI9056_INT_CTRL_STAT = %08lX\n",reg
);
528 reg
=PCICON_GET_REG(PCICON_ACK_REG
);
531 PCI_CON_PRINTF(" Alive\n");
532 PCICON_SET_REG(PCICON_DBELL_REG
,PCIMSG_ALIVE
);
535 PCI_CON_PRINTF(" Conn %d",conn
);
539 PCICON_SET_REG(PCICON_RECEIVE_REG
,0L);
541 PCI_CON_PRINTF(" ... %d\n",conn
);
543 case PCIMSG_CON_DATA
:
544 data
=PCICON_GET_REG(PCICON_RECEIVE_REG
);
545 recbuf
[w_ptr
++]=(int)(data
&0xff);
546 PCI_CON_PRINTF(" Data Console %lX, %X %d %d %X\n",data
,((int)(data
&0xFF)),
547 r_ptr
,w_ptr
,recbuf
[w_ptr
-1]);
548 if(w_ptr
==REC_BUFFER_SIZE
)
551 diff
=r_ptr
+REC_BUFFER_SIZE
-w_ptr
;
554 if(diff
>(REC_BUFFER_SIZE
-4))
558 PCICON_SET_REG(PCICON_RECEIVE_REG
,0L);
561 serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg
);
564 PCICON_SET_REG(PCICON_ACK_REG
,~0L);
569 void pci_con_connect(void)
573 reg
=PCICON_GET_REG(PCI9056_INT_CTRL_STAT
);
574 /* default 0x0f010180 */
576 reg
|= 0x00030000; /* enable local dorbell */
577 reg
|= 0x00000300; /* enable PCI dorbell */
578 PCICON_SET_REG(PCI9056_INT_CTRL_STAT
, reg
);
579 irq_install_handler (0x2, (interrupt_handler_t
*) pci_dorbell_irq
,NULL
);
580 memset (&pci_con_dev
, 0, sizeof (pci_con_dev
));
581 strcpy (pci_con_dev
.name
, "pci_con");
582 pci_con_dev
.flags
= DEV_FLAGS_OUTPUT
| DEV_FLAGS_INPUT
| DEV_FLAGS_SYSTEM
;
583 pci_con_dev
.putc
= pci_con_putc
;
584 pci_con_dev
.puts
= pci_con_puts
;
585 pci_con_dev
.getc
= pci_con_getc
;
586 pci_con_dev
.tstc
= pci_con_tstc
;
587 device_register (&pci_con_dev
);
588 printf("PATI ready for PCI connection, type ctrl-c for exit\n");
591 if((volatile int)conn
)
594 irq_free_handler(0x2);
598 console_assign(stdin
,"pci_con");
599 console_assign(stderr
,"pci_con");
600 console_assign(stdout
,"pci_con");
603 void pci_con_disc(void)
605 console_assign(stdin
,"serial");
606 console_assign(stderr
,"serial");
607 console_assign(stdout
,"serial");
608 PCICON_SET_REG(PCICON_DBELL_REG
,PCIMSG_DISC
);
610 irq_free_handler(0x02);
613 #endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */
616 * Absolute environment address for linker file.
618 GEN_ABS(env_start
, CONFIG_ENV_OFFSET
+ CONFIG_SYS_FLASH_BASE
);