3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
31 #include "../common/isa.h"
32 #include "../common/common_util.h"
34 DECLARE_GLOBAL_DATA_PTR
;
41 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
42 #ifndef __ldiv_t_defined
44 long int quot
; /* Quotient */
45 long int rem
; /* Remainder */
47 extern ldiv_t ldiv (long int __numer
, long int __denom
);
49 # define __ldiv_t_defined 1
57 SDRAM_UNSUPPORTED_ERR
,
62 const unsigned char mode
;
63 const unsigned char row
;
64 const unsigned char col
;
65 const unsigned char bank
;
68 static const SDRAM_SETUP sdram_setup_table
[] = {
87 static const unsigned char cal_indextable
[] = {
93 * translate ns.ns/10 coding of SPD timing values
94 * into 10 ps unit values
97 unsigned short NS10to10PS (unsigned char spd_byte
, unsigned char spd_version
)
99 unsigned short ns
, ns10
;
101 /* isolate upper nibble */
102 ns
= (spd_byte
>> 4) & 0x0F;
103 /* isolate lower nibble */
104 ns10
= (spd_byte
& 0x0F);
106 return (ns
* 100 + ns10
* 10);
110 * translate ns.ns/4 coding of SPD timing values
111 * into 10 ps unit values
114 unsigned short NS4to10PS (unsigned char spd_byte
, unsigned char spd_version
)
116 unsigned short ns
, ns4
;
118 /* isolate upper 6 bits */
119 ns
= (spd_byte
>> 2) & 0x3F;
120 /* isloate lower 2 bits */
121 ns4
= (spd_byte
& 0x03);
123 return (ns
* 100 + ns4
* 25);
127 * translate ns coding of SPD timing values
128 * into 10 ps unit values
131 unsigned short NSto10PS (unsigned char spd_byte
)
133 return (spd_byte
* 100);
136 void SDRAM_err (const char *s
)
139 (void) get_clocks ();
145 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
152 void write_hex (unsigned char i
)
159 serial_putc (cc
+ 55);
161 serial_putc (cc
+ 48);
164 serial_putc (cc
+ 55);
166 serial_putc (cc
+ 48);
169 void write_4hex (unsigned long val
)
171 write_hex ((unsigned char) (val
>> 24));
172 write_hex ((unsigned char) (val
>> 16));
173 write_hex ((unsigned char) (val
>> 8));
174 write_hex ((unsigned char) val
);
179 int board_early_init_f (void)
181 unsigned char dataout
[1];
182 unsigned char datain
[128];
183 unsigned long sdram_size
= 0;
184 SDRAM_SETUP
*t
= (SDRAM_SETUP
*) sdram_setup_table
;
185 unsigned long memclk
;
186 unsigned long tmemclk
= 0;
187 unsigned long tmp
, bank
, baseaddr
, bank_size
;
189 unsigned char rows
, cols
, banks
, sdram_banks
, density
;
190 unsigned char supported_cal
, trp_clocks
, trcd_clocks
, tras_clocks
,
191 trc_clocks
, tctp_clocks
;
192 unsigned char cal_index
, cal_val
, spd_version
, spd_chksum
;
193 unsigned char buf
[8];
194 /* set up the config port */
195 mtdcr (ebccfga
, pb7ap
);
196 mtdcr (ebccfgd
, CONFIG_PORT_AP
);
197 mtdcr (ebccfga
, pb7cr
);
198 mtdcr (ebccfgd
, CONFIG_PORT_CR
);
200 memclk
= get_bus_freq (tmemclk
);
201 tmemclk
= 1000000000 / (memclk
/ 100); /* in 10 ps units */
204 (void) get_clocks ();
207 serial_puts ("\nstart SDRAM Setup\n");
210 /* Read Serial Presence Detect Information */
211 i2c_init (CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
213 for (i
= 0; i
< 128; i
++)
215 i2c_read(SPD_EEPROM_ADDRESS
,0,1,datain
,128);
217 serial_puts ("\ni2c_read returns ");
223 for (i
= 0; i
< 128; i
++) {
224 write_hex (datain
[i
]);
226 if (((i
+ 1) % 16) == 0)
232 for (i
= 0; i
< 63; i
++) {
233 spd_chksum
+= datain
[i
];
235 if (datain
[63] != spd_chksum
) {
237 serial_puts ("SPD chksum: 0x");
238 write_hex (datain
[63]);
239 serial_puts (" != calc. chksum: 0x");
240 write_hex (spd_chksum
);
243 SDRAM_err ("SPD checksum Error");
245 /* SPD seems to be ok, use it */
247 /* get SPD version */
248 spd_version
= datain
[62];
250 /* do some sanity checks on the kind of RAM */
251 if ((datain
[0] < 0x80) || /* less than 128 valid bytes in SPD */
252 (datain
[2] != 0x04) || /* if not SDRAM */
253 (!((datain
[6] == 0x40) || (datain
[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
254 (datain
[7] != 0x00) || (datain
[8] != 0x01) || /* or not LVTTL signal levels */
255 (datain
[126] == 0x66)) /* or a 66Mhz modules */
256 SDRAM_err ("unsupported SDRAM");
258 serial_puts ("SDRAM sanity ok\n");
261 /* get number of rows/cols/banks out of byte 3+4+5 */
266 /* get number of SDRAM banks out of byte 17 and
267 supported CAS latencies out of byte 18 */
268 sdram_banks
= datain
[17];
269 supported_cal
= datain
[18] & ~0x81;
271 while (t
->mode
!= 0) {
272 if ((t
->row
== rows
) && (t
->col
== cols
)
273 && (t
->bank
== sdram_banks
))
279 serial_puts ("rows: ");
281 serial_puts (" cols: ");
283 serial_puts (" banks: ");
285 serial_puts (" mode: ");
290 SDRAM_err ("unsupported SDRAM");
291 /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
293 serial_puts ("tRP: ");
294 write_hex (datain
[27]);
295 serial_puts ("\ntRCD: ");
296 write_hex (datain
[29]);
297 serial_puts ("\ntRAS: ");
298 write_hex (datain
[30]);
302 trp_clocks
= (NSto10PS (datain
[27]) + (tmemclk
- 1)) / tmemclk
;
303 trcd_clocks
= (NSto10PS (datain
[29]) + (tmemclk
- 1)) / tmemclk
;
304 tras_clocks
= (NSto10PS (datain
[30]) + (tmemclk
- 1)) / tmemclk
;
305 density
= datain
[31];
307 /* trc_clocks is sum of trp_clocks + tras_clocks */
308 trc_clocks
= trp_clocks
+ tras_clocks
;
309 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
311 ((NSto10PS (datain
[30]) - NSto10PS (datain
[29])) +
312 (tmemclk
- 1)) / tmemclk
;
315 serial_puts ("c_RP: ");
316 write_hex (trp_clocks
);
317 serial_puts ("\nc_RCD: ");
318 write_hex (trcd_clocks
);
319 serial_puts ("\nc_RAS: ");
320 write_hex (tras_clocks
);
321 serial_puts ("\nc_RC: (RP+RAS): ");
322 write_hex (trc_clocks
);
323 serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
324 write_hex (tctp_clocks
);
325 serial_puts ("\nt_CTP: RAS - RCD: ");
327 char) ((NSto10PS (datain
[30]) -
328 NSto10PS (datain
[29])) >> 8));
329 write_hex ((unsigned char) (NSto10PS (datain
[30]) - NSto10PS (datain
[29])));
330 serial_puts ("\ntmemclk: ");
331 write_hex ((unsigned char) (tmemclk
>> 8));
332 write_hex ((unsigned char) (tmemclk
));
338 for (i
= 6, cal_index
= 0; (i
> 0) && (cal_index
< 3); i
--) {
339 /* is this CAS latency supported ? */
340 if ((supported_cal
>> i
) & 0x01) {
341 buf
[0] = datain
[cal_indextable
[cal_index
]];
343 if (NS10to10PS (buf
[0], spd_version
) <= tmemclk
)
346 /* SPD bytes 25+26 have another format */
347 if (NS4to10PS (buf
[0], spd_version
) <= tmemclk
)
354 serial_puts ("CAL: ");
355 write_hex (cal_val
+ 1);
360 SDRAM_err ("unsupported SDRAM");
362 /* get SDRAM timing register */
363 mtdcr (memcfga
, mem_sdtr1
);
364 tmp
= mfdcr (memcfgd
) & ~0x018FC01F;
365 /* insert CASL value */
366 /* tmp |= ((unsigned long)cal_val) << 23; */
367 tmp
|= ((unsigned long) cal_val
) << 23;
368 /* insert PTA value */
369 tmp
|= ((unsigned long) (trp_clocks
- 1)) << 18;
370 /* insert CTP value */
371 /* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
372 tmp
|= ((unsigned long) (trc_clocks
- trp_clocks
- trcd_clocks
)) << 16;
373 /* insert LDF (always 01) */
374 tmp
|= ((unsigned long) 0x01) << 14;
375 /* insert RFTA value */
376 tmp
|= ((unsigned long) (trc_clocks
- 4)) << 2;
377 /* insert RCD value */
378 tmp
|= ((unsigned long) (trcd_clocks
- 1)) << 0;
381 serial_puts ("sdtr: ");
386 /* write SDRAM timing register */
387 mtdcr (memcfga
, mem_sdtr1
);
388 mtdcr (memcfgd
, tmp
);
389 baseaddr
= CONFIG_SYS_SDRAM_BASE
;
390 bank_size
= (((unsigned long) density
) << 22) / 2;
391 /* insert AM value */
392 tmp
= ((unsigned long) t
->mode
- 1) << 13;
393 /* insert SZ value; */
396 tmp
|= ((unsigned long) 0x00) << 17;
399 tmp
|= ((unsigned long) 0x01) << 17;
402 tmp
|= ((unsigned long) 0x02) << 17;
405 tmp
|= ((unsigned long) 0x03) << 17;
408 tmp
|= ((unsigned long) 0x04) << 17;
411 tmp
|= ((unsigned long) 0x05) << 17;
414 tmp
|= ((unsigned long) 0x06) << 17;
417 SDRAM_err ("unsupported SDRAM");
419 /* get SDRAM bank 0 register */
420 mtdcr (memcfga
, mem_mb0cf
);
421 bank
= mfdcr (memcfgd
) & ~0xFFCEE001;
422 bank
|= (baseaddr
| tmp
| 0x01);
424 serial_puts ("bank0: baseaddr: ");
425 write_4hex (baseaddr
);
426 serial_puts (" banksize: ");
427 write_4hex (bank_size
);
428 serial_puts (" mb0cf: ");
432 baseaddr
+= bank_size
;
433 sdram_size
+= bank_size
;
435 /* write SDRAM bank 0 register */
436 mtdcr (memcfga
, mem_mb0cf
);
437 mtdcr (memcfgd
, bank
);
439 /* get SDRAM bank 1 register */
440 mtdcr (memcfga
, mem_mb1cf
);
441 bank
= mfdcr (memcfgd
) & ~0xFFCEE001;
445 serial_puts ("bank1: baseaddr: ");
446 write_4hex (baseaddr
);
447 serial_puts (" banksize: ");
448 write_4hex (bank_size
);
451 bank
|= (baseaddr
| tmp
| 0x01);
452 baseaddr
+= bank_size
;
453 sdram_size
+= bank_size
;
456 serial_puts (" mb1cf: ");
460 /* write SDRAM bank 1 register */
461 mtdcr (memcfga
, mem_mb1cf
);
462 mtdcr (memcfgd
, bank
);
464 /* get SDRAM bank 2 register */
465 mtdcr (memcfga
, mem_mb2cf
);
466 bank
= mfdcr (memcfgd
) & ~0xFFCEE001;
468 bank
|= (baseaddr
| tmp
| 0x01);
471 serial_puts ("bank2: baseaddr: ");
472 write_4hex (baseaddr
);
473 serial_puts (" banksize: ");
474 write_4hex (bank_size
);
475 serial_puts (" mb2cf: ");
480 baseaddr
+= bank_size
;
481 sdram_size
+= bank_size
;
483 /* write SDRAM bank 2 register */
484 mtdcr (memcfga
, mem_mb2cf
);
485 mtdcr (memcfgd
, bank
);
487 /* get SDRAM bank 3 register */
488 mtdcr (memcfga
, mem_mb3cf
);
489 bank
= mfdcr (memcfgd
) & ~0xFFCEE001;
492 serial_puts ("bank3: baseaddr: ");
493 write_4hex (baseaddr
);
494 serial_puts (" banksize: ");
495 write_4hex (bank_size
);
499 bank
|= (baseaddr
| tmp
| 0x01);
500 baseaddr
+= bank_size
;
501 sdram_size
+= bank_size
;
505 serial_puts (" mb3cf: ");
510 /* write SDRAM bank 3 register */
511 mtdcr (memcfga
, mem_mb3cf
);
512 mtdcr (memcfgd
, bank
);
515 /* get SDRAM refresh interval register */
516 mtdcr (memcfga
, mem_rtr
);
517 tmp
= mfdcr (memcfgd
) & ~0x3FF80000;
519 if (tmemclk
< NSto10PS (16))
524 /* write SDRAM refresh interval register */
525 mtdcr (memcfga
, mem_rtr
);
526 mtdcr (memcfgd
, tmp
);
528 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
529 mtdcr (memcfga
, mem_mcopt1
);
530 tmp
= (mfdcr (memcfgd
) & ~0xFFE00000) | 0x80E00000;
531 mtdcr (memcfga
, mem_mcopt1
);
532 mtdcr (memcfgd
, tmp
);
535 /*-------------------------------------------------------------------------+
536 | Interrupt controller setup for the PIP405 board.
537 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
538 | IRQ 16 405GP internally generated; active low; level sensitive
540 | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
541 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
542 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
543 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
544 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
545 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
546 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
547 | Note for PIP405 board:
548 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
549 | the Interrupt Controller in the South Bridge has caused the
550 | interrupt. The IC must be read to determine which device
551 | caused the interrupt.
553 +-------------------------------------------------------------------------*/
554 mtdcr (uicsr
, 0xFFFFFFFF); /* clear all ints */
555 mtdcr (uicer
, 0x00000000); /* disable all ints */
556 mtdcr (uiccr
, 0x00000000); /* set all to be non-critical (for now) */
557 mtdcr (uicpr
, 0xFFFFFF80); /* set int polarities */
558 mtdcr (uictr
, 0x10000000); /* set int trigger levels */
559 mtdcr (uicvcr
, 0x00000001); /* set vect base=0,INT0 highest priority */
560 mtdcr (uicsr
, 0xFFFFFFFF); /* clear all ints */
566 /* ------------------------------------------------------------------------- */
569 * Check Board Identity:
572 int checkboard (void)
577 backup_t
*b
= (backup_t
*) s
;
581 i
= getenv_r ("serial#", (char *)s
, 32);
582 if ((i
== 0) || strncmp ((char *)s
, "PIP405", 6)) {
583 get_backup_values (b
);
584 if (strncmp (b
->signature
, "MPL\0", 4) != 0) {
585 puts ("### No HW ID - assuming PIP405");
587 b
->serial_name
[6] = 0;
588 printf ("%s SN: %s", b
->serial_name
,
593 printf ("%s SN: %s", s
, &s
[7]);
595 bc
= in8 (CONFIG_PORT_ADDR
);
596 printf (" Boot Config: 0x%x\n", bc
);
601 /* ------------------------------------------------------------------------- */
602 /* ------------------------------------------------------------------------- */
604 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
605 the necessary info for SDRAM controller configuration
607 /* ------------------------------------------------------------------------- */
608 /* ------------------------------------------------------------------------- */
609 static int test_dram (unsigned long ramsize
);
611 phys_size_t
initdram (int board_type
)
613 unsigned long bank_reg
[4], tmp
, bank_size
;
615 unsigned long TotalSize
;
618 /* since the DRAM controller is allready set up,
619 * calculate the size with the bank registers
621 mtdcr (memcfga
, mem_mb0cf
);
622 bank_reg
[0] = mfdcr (memcfgd
);
623 mtdcr (memcfga
, mem_mb1cf
);
624 bank_reg
[1] = mfdcr (memcfgd
);
625 mtdcr (memcfga
, mem_mb2cf
);
626 bank_reg
[2] = mfdcr (memcfgd
);
627 mtdcr (memcfga
, mem_mb3cf
);
628 bank_reg
[3] = mfdcr (memcfgd
);
630 for (i
= 0; i
< 4; i
++) {
631 if ((bank_reg
[i
] & 0x1) == 0x1) {
632 tmp
= (bank_reg
[i
] >> 17) & 0x7;
633 bank_size
= 4 << tmp
;
634 TotalSize
+= bank_size
;
639 printf ("single-sided DIMM ");
641 printf ("double-sided DIMM ");
642 test_dram (TotalSize
* 1024 * 1024);
643 /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
645 if (gd
->cpu_clk
> 220000000)
647 return (TotalSize
* 1024 * 1024);
650 /* ------------------------------------------------------------------------- */
653 static int test_dram (unsigned long ramsize
)
655 /* not yet implemented */
660 extern flash_info_t flash_info
[]; /* info for FLASH chips */
662 int misc_init_r (void)
664 /* adjust flash start and size as well as the offset */
665 gd
->bd
->bi_flashstart
=0-flash_info
[0].size
;
666 gd
->bd
->bi_flashsize
=flash_info
[0].size
-CONFIG_SYS_MONITOR_LEN
;
667 gd
->bd
->bi_flashoffset
=0;
669 /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
670 if (mfdcr(strap
) & PSR_ROM_LOC
)
671 mtspr(ccr0
, (mfspr(ccr0
) & ~0x80));
676 /***************************************************************************
677 * some helping routines
680 int overwrite_console (void)
682 return (in8 (CONFIG_PORT_ADDR
) & 0x1); /* return TRUE if console should be overwritten */
686 extern int isa_init (void);
689 void print_pip405_rev (void)
691 unsigned char part
, vers
, cfg
;
693 part
= in8 (PLD_PART_REG
);
694 vers
= in8 (PLD_VERS_REG
);
695 cfg
= in8 (PLD_BOARD_CFG_REG
);
696 printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
697 16 - ((cfg
>> 4) & 0xf), (cfg
& 0xf) + 'A', part
& 0xf,
698 vers
& 0xf, (part
>> 4) & 0xf, (vers
>> 4) & 0xf);
701 extern void check_env(void);
704 int last_stage_init (void)
713 /************************************************************************
715 ************************************************************************/
716 void print_pip405_info (void)
718 unsigned char part
, vers
, cfg
, ledu
, sysman
, flashcom
, can
, serpwr
,
719 compwr
, nicvga
, scsirst
;
721 part
= in8 (PLD_PART_REG
);
722 vers
= in8 (PLD_VERS_REG
);
723 cfg
= in8 (PLD_BOARD_CFG_REG
);
724 ledu
= in8 (PLD_LED_USER_REG
);
725 sysman
= in8 (PLD_SYS_MAN_REG
);
726 flashcom
= in8 (PLD_FLASH_COM_REG
);
727 can
= in8 (PLD_CAN_REG
);
728 serpwr
= in8 (PLD_SER_PWR_REG
);
729 compwr
= in8 (PLD_COM_PWR_REG
);
730 nicvga
= in8 (PLD_NIC_VGA_REG
);
731 scsirst
= in8 (PLD_SCSI_RST_REG
);
732 printf ("PLD Part %d version %d\n",
733 part
& 0xf, vers
& 0xf);
734 printf ("PLD Part %d version %d\n",
735 (part
>> 4) & 0xf, (vers
>> 4) & 0xf);
736 printf ("Board Revision %c\n", (cfg
& 0xf) + 'A');
737 printf ("Population Options %d %d %d %d\n",
738 (cfg
>> 4) & 0x1, (cfg
>> 5) & 0x1,
739 (cfg
>> 6) & 0x1, (cfg
>> 7) & 0x1);
740 printf ("User LED0 %s User LED1 %s\n",
741 ((ledu
& 0x1) == 0x1) ? "on" : "off",
742 ((ledu
& 0x2) == 0x2) ? "on" : "off");
743 printf ("Additionally Options %d %d\n",
744 (ledu
>> 2) & 0x1, (ledu
>> 3) & 0x1);
745 printf ("User Config Switch %d %d %d %d\n",
746 (ledu
>> 4) & 0x1, (ledu
>> 5) & 0x1,
747 (ledu
>> 6) & 0x1, (ledu
>> 7) & 0x1);
748 switch (sysman
& 0x3) {
750 printf ("PCI Clocks are running\n");
753 printf ("PCI Clocks are stopped in POS State\n");
756 printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
759 printf ("PCI Clocks are stopped\n");
762 switch ((sysman
>> 2) & 0x3) {
764 printf ("Main Clocks are running\n");
767 printf ("Main Clocks are stopped in POS State\n");
771 printf ("PCI Clocks are stopped\n");
774 printf ("INIT asserts %sINT2# (SMI)\n",
775 ((sysman
& 0x10) == 0x10) ? "" : "not ");
776 printf ("INIT asserts %sINT1# (NMI)\n",
777 ((sysman
& 0x20) == 0x20) ? "" : "not ");
778 printf ("INIT occured %d\n", (sysman
>> 6) & 0x1);
779 printf ("SER1 is routed to %s\n",
780 ((flashcom
& 0x1) == 0x1) ? "RS485" : "RS232");
781 printf ("COM2 is routed to %s\n",
782 ((flashcom
& 0x2) == 0x2) ? "RS485" : "RS232");
783 printf ("RS485 is configured as %s duplex\n",
784 ((flashcom
& 0x4) == 0x4) ? "full" : "half");
785 printf ("RS485 is connected to %s\n",
786 ((flashcom
& 0x8) == 0x8) ? "COM1" : "COM2");
787 printf ("SER1 uses handshakes %s\n",
788 ((flashcom
& 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
789 printf ("Bootflash is %swriteprotected\n",
790 ((flashcom
& 0x20) == 0x20) ? "not " : "");
791 printf ("Bootflash VPP is %s\n",
792 ((flashcom
& 0x40) == 0x40) ? "on" : "off");
793 printf ("Bootsector is %swriteprotected\n",
794 ((flashcom
& 0x80) == 0x80) ? "not " : "");
795 switch ((can
) & 0x3) {
797 printf ("CAN Controller is on address 0x1000..0x10FF\n");
800 printf ("CAN Controller is on address 0x8000..0x80FF\n");
803 printf ("CAN Controller is on address 0xE000..0xE0FF\n");
806 printf ("CAN Controller is disabled\n");
809 switch ((can
>> 2) & 0x3) {
811 printf ("CAN Controller Reset is ISA Reset\n");
814 printf ("CAN Controller Reset is ISA Reset and POS State\n");
818 printf ("CAN Controller is in reset\n");
821 if (((can
>> 4) < 3) || ((can
>> 4) == 8) || ((can
>> 4) == 13))
822 printf ("CAN Interrupt is disabled\n");
824 printf ("CAN Interrupt is ISA INT%d\n", (can
>> 4) & 0xf);
825 switch (serpwr
& 0x3) {
827 printf ("SER0 Drivers are enabled\n");
830 printf ("SER0 Drivers are disabled in the POS state\n");
834 printf ("SER0 Drivers are disabled\n");
837 switch ((serpwr
>> 2) & 0x3) {
839 printf ("SER1 Drivers are enabled\n");
842 printf ("SER1 Drivers are disabled in the POS state\n");
846 printf ("SER1 Drivers are disabled\n");
849 switch (compwr
& 0x3) {
851 printf ("COM1 Drivers are enabled\n");
854 printf ("COM1 Drivers are disabled in the POS state\n");
858 printf ("COM1 Drivers are disabled\n");
861 switch ((compwr
>> 2) & 0x3) {
863 printf ("COM2 Drivers are enabled\n");
866 printf ("COM2 Drivers are disabled in the POS state\n");
870 printf ("COM2 Drivers are disabled\n");
873 switch ((nicvga
) & 0x3) {
875 printf ("PHY is running\n");
878 printf ("PHY is in Power save mode in POS state\n");
882 printf ("PHY is in Power save mode\n");
885 switch ((nicvga
>> 2) & 0x3) {
887 printf ("VGA is running\n");
890 printf ("VGA is in Power save mode in POS state\n");
894 printf ("VGA is in Power save mode\n");
897 printf ("PHY is %sreseted\n", ((nicvga
& 0x10) == 0x10) ? "" : "not ");
898 printf ("VGA is %sreseted\n", ((nicvga
& 0x20) == 0x20) ? "" : "not ");
899 printf ("Reserved Configuration is %d %d\n", (nicvga
>> 6) & 0x1,
900 (nicvga
>> 7) & 0x1);
901 switch ((scsirst
) & 0x3) {
903 printf ("SCSI Controller is running\n");
906 printf ("SCSI Controller is in Power save mode in POS state\n");
910 printf ("SCSI Controller is in Power save mode\n");
913 printf ("SCSI termination is %s\n",
914 ((scsirst
& 0x4) == 0x4) ? "disabled" : "enabled");
915 printf ("SCSI Controller is %sreseted\n",
916 ((scsirst
& 0x10) == 0x10) ? "" : "not ");
917 printf ("IDE disks are %sreseted\n",
918 ((scsirst
& 0x20) == 0x20) ? "" : "not ");
919 printf ("ISA Bus is %sreseted\n",
920 ((scsirst
& 0x40) == 0x40) ? "" : "not ");
921 printf ("Super IO is %sreseted\n",
922 ((scsirst
& 0x80) == 0x80) ? "" : "not ");
925 void user_led0 (unsigned char on
)
928 out8 (PLD_LED_USER_REG
, (in8 (PLD_LED_USER_REG
) | 0x1));
930 out8 (PLD_LED_USER_REG
, (in8 (PLD_LED_USER_REG
) & 0xfe));
933 void user_led1 (unsigned char on
)
936 out8 (PLD_LED_USER_REG
, (in8 (PLD_LED_USER_REG
) | 0x2));
938 out8 (PLD_LED_USER_REG
, (in8 (PLD_LED_USER_REG
) & 0xfd));
941 void ide_set_reset (int idereset
)
943 /* if reset = 1 IDE reset will be asserted */
944 unsigned char resreg
;
946 resreg
= in8 (PLD_SCSI_RST_REG
);
953 out8 (PLD_SCSI_RST_REG
, resreg
);