2 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * Memory Controller Using
32 * CS0 - Flash memory (0x40000000)
33 * CS3 - SDRAM (0x00000000}
36 /* ------------------------------------------------------------------------- */
38 #define _not_used_ 0xffffffff
40 const uint sdram_table
[] = {
41 /* single read. (offset 0 in upm RAM) */
42 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
45 /* MRS initialization (offset 5) */
47 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
49 /* burst read. (offset 8 in upm RAM) */
50 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
51 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
52 _not_used_
, _not_used_
, _not_used_
, _not_used_
,
53 _not_used_
, _not_used_
, _not_used_
, _not_used_
,
55 /* single write. (offset 18 in upm RAM) */
56 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
57 _not_used_
, _not_used_
, _not_used_
, _not_used_
,
59 /* burst write. (offset 20 in upm RAM) */
60 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
61 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_
,
62 _not_used_
, _not_used_
, _not_used_
, _not_used_
,
63 _not_used_
, _not_used_
, _not_used_
, _not_used_
,
65 /* refresh. (offset 30 in upm RAM) */
66 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
67 0xfffffc84, 0xfffffc07, _not_used_
, _not_used_
,
68 _not_used_
, _not_used_
, _not_used_
, _not_used_
,
70 /* exception. (offset 3c in upm RAM) */
71 0x7ffffc07, _not_used_
, _not_used_
, _not_used_
74 const uint nand_flash_table
[] = {
75 /* single read. (offset 0 in upm RAM) */
76 0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04,
77 0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05,
79 /* burst read. (offset 8 in upm RAM) */
80 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
81 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
82 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
83 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
85 /* single write. (offset 18 in upm RAM) */
86 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04,
87 0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05,
89 /* burst write. (offset 20 in upm RAM) */
90 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
91 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
92 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
93 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
95 /* refresh. (offset 30 in upm RAM) */
96 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
97 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
98 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
100 /* exception. (offset 3c in upm RAM) */
101 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05
104 /* ------------------------------------------------------------------------- */
107 * Check Board Identity:
110 int checkboard (void)
112 #if !defined(CONFIG_CP850)
113 puts ("Board: NC650");
115 puts ("Board: CP850");
117 #if defined(CONFIG_IDS852_REV1)
118 puts (" with IDS852 rev 1 module\n");
119 #elif defined(CONFIG_IDS852_REV2)
120 puts (" with IDS852 rev 2 module\n");
125 /* ------------------------------------------------------------------------- */
127 static long int dram_size (long int, long int *, long int);
129 /* ------------------------------------------------------------------------- */
131 phys_size_t
initdram (int board_type
)
133 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
134 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
135 long int size8
, size9
;
136 long int size_b0
= 0;
139 upmconfig (UPMA
, (uint
*) sdram_table
,
140 sizeof (sdram_table
) / sizeof (uint
));
143 * Preliminary prescaler for refresh (depends on number of
144 * banks): This value is selected for four cycles every 62.4 us
145 * with two SDRAM banks or four cycles every 31.2 us with one
146 * bank. It will be adjusted after memory sizing.
148 memctl
->memc_mptpr
= CONFIG_SYS_MPTPR_2BK_8K
;
150 memctl
->memc_mar
= 0x00000088;
153 * Map controller bank 1 to the SDRAM bank at
154 * preliminary address - these have to be modified after the
155 * SDRAM size has been determined.
157 memctl
->memc_or3
= CONFIG_SYS_OR3_PRELIM
;
158 memctl
->memc_br3
= CONFIG_SYS_BR3_PRELIM
;
160 memctl
->memc_mamr
= CONFIG_SYS_MAMR_8COL
& (~(MAMR_PTAE
)); /* no refresh yet */
164 /* perform SDRAM initializsation sequence */
166 memctl
->memc_mcr
= 0x80006105; /* SDRAM bank 0 */
168 memctl
->memc_mcr
= 0x80006230; /* SDRAM bank 0 - execute twice */
171 memctl
->memc_mamr
|= MAMR_PTAE
; /* enable refresh */
176 * Check Bank 0 Memory Size for re-configuration
180 size8
= dram_size (CONFIG_SYS_MAMR_8COL
, SDRAM_BASE3_PRELIM
, SDRAM_MAX_SIZE
);
187 size9
= dram_size (CONFIG_SYS_MAMR_9COL
, SDRAM_BASE3_PRELIM
, SDRAM_MAX_SIZE
);
195 memctl
->memc_mamr
= CONFIG_SYS_MAMR_8COL
;
200 * Adjust refresh rate depending on SDRAM type, both banks.
201 * For types > 128 MBit leave it at the current (fast) rate
203 if ((size_b0
< 0x02000000)) {
204 /* reduce to 15.6 us (62.4 us / quad) */
205 memctl
->memc_mptpr
= CONFIG_SYS_MPTPR_2BK_4K
;
213 memctl
->memc_or3
= ((-size_b0
) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM
;
214 memctl
->memc_br3
= (CONFIG_SYS_SDRAM_BASE
& BR_BA_MSK
) | BR_MS_UPMA
| BR_V
;
216 /* adjust refresh rate depending on SDRAM type, one bank */
217 reg
= memctl
->memc_mptpr
;
218 reg
>>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
219 memctl
->memc_mptpr
= reg
;
223 /* Configure UPMB for NAND flash access */
224 upmconfig (UPMB
, (uint
*) nand_flash_table
,
225 sizeof (nand_flash_table
) / sizeof (uint
));
227 memctl
->memc_mbmr
= CONFIG_SYS_MBMR_NAND
;
232 /* ------------------------------------------------------------------------- */
235 * Check memory range for valid RAM. A simple memory test determines
236 * the actually available RAM size between addresses `base' and
237 * `base + maxsize'. Some (not all) hardware errors are detected:
238 * - short between address lines
239 * - short between data lines
242 static long int dram_size (long int mamr_value
, long int *base
, long int maxsize
)
244 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
245 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
247 memctl
->memc_mamr
= mamr_value
;
249 return (get_ram_size(base
, maxsize
));
253 #if defined(CONFIG_CP850)
255 #define DPRAM_VARNAME "KP850DIP"
256 #define PARAM_ADDR 0x7C0
257 #define NAME_ADDR 0x7F8
258 #define BOARD_NAME "KP01"
259 #define DEFAULT_LB "241111"
261 int misc_init_r(void)
268 First byte in CPLD read address space signals compatibility mode
272 pParam
= (char*)(CONFIG_SYS_CPLD_BASE
);
276 if ( iCompatMode
!= 0) {
278 In KP852 compatibility mode we have to write to
279 DPRAM as early as possible the binary coded
280 line config and board name.
281 The line config is derived from the environment
282 variable DPRAM_VARNAME by converting from ASCII
283 to binary per character.
285 if ( (envlb
= getenv ( DPRAM_VARNAME
)) == 0) {
286 setenv( DPRAM_VARNAME
, DEFAULT_LB
);
291 printf("Mode: KP852(LB=%s)\n", envlb
);
294 pParam
= (char*)(DPRAM_BASE_ADDR
+ PARAM_ADDR
);
296 *(pParam
++) = *(envlb
++) - '0';
301 pParam
= (char*)(DPRAM_BASE_ADDR
+ NAME_ADDR
);
302 strcpy( pParam
, BOARD_NAME
);
304 puts("Mode: CP850\n");