board/netta/netta.c

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
  26  * U-Boot port on NetTA4 board
  27  */
  28
  29 #include <common.h>
  30 #include <miiphy.h>
  31
  32 #include "mpc8xx.h"
  33
  34 #ifdef CONFIG_HW_WATCHDOG
  35 #include <watchdog.h>
  36 #endif
  37
  38 /****************************************************************/
  39
  40 /* some sane bit macros */
  41 #define _BD(_b)                         (1U << (31-(_b)))
  42 #define _BDR(_l, _h)                    (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
  43
  44 #define _BW(_b)                         (1U << (15-(_b)))
  45 #define _BWR(_l, _h)                    (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
  46
  47 #define _BB(_b)                         (1U << (7-(_b)))
  48 #define _BBR(_l, _h)                    (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
  49
  50 #define _B(_b)                          _BD(_b)
  51 #define _BR(_l, _h)                     _BDR(_l, _h)
  52
  53 /****************************************************************/
  54
  55 /*
  56  * Check Board Identity:
  57  *
  58  * Return 1 always.
  59  */
  60
  61 int checkboard(void)
  62 {
  63         printf ("Intracom NETTA"
  64 #if defined(CONFIG_NETTA_ISDN)
  65                         " with ISDN support"
  66 #endif
  67                         "\n"
  68                         );
  69         return (0);
  70 }
  71
  72 /****************************************************************/
  73
  74 #define _NOT_USED_      0xFFFFFFFF
  75
  76 /****************************************************************/
  77
  78 #define CS_0000         0x00000000
  79 #define CS_0001         0x10000000
  80 #define CS_0010         0x20000000
  81 #define CS_0011         0x30000000
  82 #define CS_0100         0x40000000
  83 #define CS_0101         0x50000000
  84 #define CS_0110         0x60000000
  85 #define CS_0111         0x70000000
  86 #define CS_1000         0x80000000
  87 #define CS_1001         0x90000000
  88 #define CS_1010         0xA0000000
  89 #define CS_1011         0xB0000000
  90 #define CS_1100         0xC0000000
  91 #define CS_1101         0xD0000000
  92 #define CS_1110         0xE0000000
  93 #define CS_1111         0xF0000000
  94
  95 #define BS_0000         0x00000000
  96 #define BS_0001         0x01000000
  97 #define BS_0010         0x02000000
  98 #define BS_0011         0x03000000
  99 #define BS_0100         0x04000000
 100 #define BS_0101         0x05000000
 101 #define BS_0110         0x06000000
 102 #define BS_0111         0x07000000
 103 #define BS_1000         0x08000000
 104 #define BS_1001         0x09000000
 105 #define BS_1010         0x0A000000
 106 #define BS_1011         0x0B000000
 107 #define BS_1100         0x0C000000
 108 #define BS_1101         0x0D000000
 109 #define BS_1110         0x0E000000
 110 #define BS_1111         0x0F000000
 111
 112 #define A10_AAAA        0x00000000
 113 #define A10_AAA0        0x00200000
 114 #define A10_AAA1        0x00300000
 115 #define A10_000A        0x00800000
 116 #define A10_0000        0x00A00000
 117 #define A10_0001        0x00B00000
 118 #define A10_111A        0x00C00000
 119 #define A10_1110        0x00E00000
 120 #define A10_1111        0x00F00000
 121
 122 #define RAS_0000        0x00000000
 123 #define RAS_0001        0x00040000
 124 #define RAS_1110        0x00080000
 125 #define RAS_1111        0x000C0000
 126
 127 #define CAS_0000        0x00000000
 128 #define CAS_0001        0x00010000
 129 #define CAS_1110        0x00020000
 130 #define CAS_1111        0x00030000
 131
 132 #define WE_0000         0x00000000
 133 #define WE_0001         0x00004000
 134 #define WE_1110         0x00008000
 135 #define WE_1111         0x0000C000
 136
 137 #define GPL4_0000       0x00000000
 138 #define GPL4_0001       0x00001000
 139 #define GPL4_1110       0x00002000
 140 #define GPL4_1111       0x00003000
 141
 142 #define GPL5_0000       0x00000000
 143 #define GPL5_0001       0x00000400
 144 #define GPL5_1110       0x00000800
 145 #define GPL5_1111       0x00000C00
 146 #define LOOP            0x00000080
 147
 148 #define EXEN            0x00000040
 149
 150 #define AMX_COL         0x00000000
 151 #define AMX_ROW         0x00000020
 152 #define AMX_MAR         0x00000030
 153
 154 #define NA              0x00000008
 155
 156 #define UTA             0x00000004
 157
 158 #define TODT            0x00000002
 159
 160 #define LAST            0x00000001
 161
 162 /* #define CAS_LATENCY  3 */
 163 #define CAS_LATENCY     2
 164
 165 const uint sdram_table[0x40] = {
 166
 167 #if CAS_LATENCY == 3
 168         /* RSS */
 169         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 170         CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 171         CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 172         CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 173         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 174         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 175         _NOT_USED_, _NOT_USED_,
 176
 177         /* RBS */
 178         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 179         CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 180         CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 181         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 182         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 183         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 184         CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,                         /* PALL  */
 185         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,           /* NOP   */
 186         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 187         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 188
 189         /* WSS */
 190         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 191         CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 192         CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
 193         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 194         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 195         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 196
 197         /* WBS */
 198         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 199         CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 200         CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,                         /* WRITE */
 201         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 202         CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 203         CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 204         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 205         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 206         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 207         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 208         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 209 #endif
 210
 211 #if CAS_LATENCY == 2
 212         /* RSS */
 213         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 214         CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 215         CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 216         CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
 217         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 218         _NOT_USED_,
 219         _NOT_USED_, _NOT_USED_,
 220
 221         /* RBS */
 222         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 223         CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 224         CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 225         CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 226         CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 227         CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 228         CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
 229         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 230         _NOT_USED_,
 231         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 232         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 233
 234         /* WSS */
 235         CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 236         CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
 237         CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
 238         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 239         _NOT_USED_,
 240         _NOT_USED_, _NOT_USED_,
 241         _NOT_USED_,
 242
 243         /* WBS */
 244         CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 245         CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
 246         CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,                         /* WRITE */
 247         CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 248         CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 249         CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,                   /* NOP   */
 250         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 251         _NOT_USED_,
 252         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 253         _NOT_USED_, _NOT_USED_, _NOT_USED_,
 254         _NOT_USED_, _NOT_USED_,
 255
 256 #endif
 257
 258         /* UPT */
 259         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,            /* ATRFR */
 260         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 261         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 262         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 263         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,            /* NOP   */
 264         CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 265         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 266         _NOT_USED_, _NOT_USED_,
 267
 268         /* EXC */
 269         CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
 270         _NOT_USED_,
 271
 272         /* REG */
 273         CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
 274         CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
 275 };
 276
 277 /* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
 278 /* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
 279 #define MAR_SDRAM_INIT          ((CAS_LATENCY << 6) | 0x00000008LU)
 280
 281 /* 8 */
 282 #define CFG_MAMR        ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 283                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 284                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 285
 286 void check_ram(unsigned int addr, unsigned int size)
 287 {
 288         unsigned int i, j, v, vv;
 289         volatile unsigned int *p;
 290         unsigned int pv;
 291
 292         p = (unsigned int *)addr;
 293         pv = (unsigned int)p;
 294         for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
 295                 *p++ = pv;
 296
 297         p = (unsigned int *)addr;
 298         for (i = 0; i < size / sizeof(unsigned int); i++) {
 299                 v = (unsigned int)p;
 300                 vv = *p;
 301                 if (vv != v) {
 302                         printf("%p: read %08x instead of %08x\n", p, vv, v);
 303                         hang();
 304                 }
 305                 p++;
 306         }
 307
 308         for (j = 0; j < 5; j++) {
 309                 switch (j) {
 310                         case 0: v = 0x00000000; break;
 311                         case 1: v = 0xffffffff; break;
 312                         case 2: v = 0x55555555; break;
 313                         case 3: v = 0xaaaaaaaa; break;
 314                         default:v = 0xdeadbeef; break;
 315                 }
 316                 p = (unsigned int *)addr;
 317                 for (i = 0; i < size / sizeof(unsigned int); i++) {
 318                         *p = v;
 319                         vv = *p;
 320                         if (vv != v) {
 321                                 printf("%p: read %08x instead of %08x\n", p, vv, v);
 322                                 hang();
 323                         }
 324                         *p = ~v;
 325                         p++;
 326                 }
 327         }
 328 }
 329
 330 long int initdram(int board_type)
 331 {
 332         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 333         volatile memctl8xx_t *memctl = &immap->im_memctl;
 334         long int size;
 335
 336         upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
 337
 338         /*
 339          * Preliminary prescaler for refresh
 340          */
 341         memctl->memc_mptpr = MPTPR_PTP_DIV8;
 342
 343         memctl->memc_mar = MAR_SDRAM_INIT;      /* 32-bit address to be output on the address bus if AMX = 0b11 */
 344
 345         /*
 346          * Map controller bank 3 to the SDRAM bank at preliminary address.
 347          */
 348         memctl->memc_or3 = CFG_OR3_PRELIM;
 349         memctl->memc_br3 = CFG_BR3_PRELIM;
 350
 351         memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE;      /* no refresh yet */
 352
 353         udelay(200);
 354
 355         /* perform SDRAM initialisation sequence */
 356         memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);   /* precharge all                */
 357         udelay(1);
 358
 359         memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);   /* refresh 2 times(0)           */
 360         udelay(1);
 361
 362         memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);   /* exception program (write mar)*/
 363         udelay(1);
 364
 365         memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
 366
 367         udelay(10000);
 368
 369         {
 370                 u32 d1, d2;
 371
 372                 d1 = 0xAA55AA55;
 373                 *(volatile u32 *)0 = d1;
 374                 d2 = *(volatile u32 *)0;
 375                 if (d1 != d2) {
 376                         printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
 377                         hang();
 378                 }
 379
 380                 d1 = 0x55AA55AA;
 381                 *(volatile u32 *)0 = d1;
 382                 d2 = *(volatile u32 *)0;
 383                 if (d1 != d2) {
 384                         printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
 385                         hang();
 386                 }
 387         }
 388
 389         size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
 390
 391 #if 0
 392         printf("check 0\n");
 393         check_ram(( 0 << 20), (2 << 20));
 394         printf("check 16\n");
 395         check_ram((16 << 20), (2 << 20));
 396         printf("check 32\n");
 397         check_ram((32 << 20), (2 << 20));
 398         printf("check 48\n");
 399         check_ram((48 << 20), (2 << 20));
 400 #endif
 401
 402         if (size == 0) {
 403                 printf("SIZE is zero: LOOP on 0\n");
 404                 for (;;) {
 405                         *(volatile u32 *)0 = 0;
 406                         (void)*(volatile u32 *)0;
 407                 }
 408         }
 409
 410         return size;
 411 }
 412
 413 /* ------------------------------------------------------------------------- */
 414
 415 int misc_init_r(void)
 416 {
 417         return(0);
 418 }
 419
 420 void reset_phys(void)
 421 {
 422         int phyno;
 423         unsigned short v;
 424
 425         /* reset the damn phys */
 426         mii_init();
 427
 428         for (phyno = 0; phyno < 32; ++phyno) {
 429                 miiphy_read(phyno, PHY_PHYIDR1, &v);
 430                 if (v == 0xFFFF)
 431                         continue;
 432                 miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
 433                 udelay(10000);
 434                 miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
 435                 udelay(10000);
 436         }
 437 }
 438
 439 extern int board_dsp_reset(void);
 440
 441 int last_stage_init(void)
 442 {
 443         int r;
 444
 445         reset_phys();
 446         r = board_dsp_reset();
 447         if (r < 0)
 448                 printf("*** WARNING *** DSP reset failed (run diagnostics)\n");
 449         return 0;
 450 }
 451
 452 /* ------------------------------------------------------------------------- */
 453
 454 /* GP = general purpose, SP = special purpose (on chip peripheral) */
 455
 456 /* bits that can have a special purpose or can be configured as inputs/outputs */
 457 #define PA_GP_INMASK    (_BWR(3) | _BWR(7, 9) | _BW(11))
 458 #define PA_GP_OUTMASK   (_BW(6) | _BW(10) | _BWR(12, 15))
 459 #define PA_SP_MASK      (_BWR(0, 2) | _BWR(4, 5))
 460 #define PA_ODR_VAL      0
 461 #define PA_GP_OUTVAL    (_BW(13) | _BWR(14, 15))
 462 #define PA_SP_DIRVAL    0
 463
 464 #define PB_GP_INMASK    (_B(28) | _B(31))
 465 #define PB_GP_OUTMASK   (_BR(16, 19) | _BR(26, 27) | _BR(29, 30))
 466 #define PB_SP_MASK      (_BR(22, 25))
 467 #define PB_ODR_VAL      0
 468 #define PB_GP_OUTVAL    (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
 469 #define PB_SP_DIRVAL    0
 470
 471 #define PC_GP_INMASK    (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
 472 #define PC_GP_OUTMASK   (_BW(6) | _BW(12))
 473 #define PC_SP_MASK      (_BW(4) | _BW(8))
 474 #define PC_SOVAL        0
 475 #define PC_INTVAL       _BW(7)
 476 #define PC_GP_OUTVAL    (_BW(6) | _BW(12))
 477 #define PC_SP_DIRVAL    0
 478
 479 #define PD_GP_INMASK    0
 480 #define PD_GP_OUTMASK   _BWR(3, 15)
 481 #define PD_SP_MASK      0
 482 #define PD_GP_OUTVAL    (_BWR(5, 7) | _BW(9) | _BW(11))
 483 #define PD_SP_DIRVAL    0
 484
 485 int board_early_init_f(void)
 486 {
 487         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 488         volatile iop8xx_t *ioport = &immap->im_ioport;
 489         volatile cpm8xx_t *cpm = &immap->im_cpm;
 490         volatile memctl8xx_t *memctl = &immap->im_memctl;
 491
 492         /* CS1: NAND chip select */
 493         memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
 494         memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 495
 496         /* CS2: DSP */
 497         memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
 498         memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
 499
 500         /* CS4: External register chip select */
 501         memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
 502         memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
 503
 504         /* CS5: dummy for accurate delay */
 505         memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2);
 506         memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
 507
 508         ioport->iop_padat       = PA_GP_OUTVAL;
 509         ioport->iop_paodr       = PA_ODR_VAL;
 510         ioport->iop_padir       = PA_GP_OUTMASK | PA_SP_DIRVAL;
 511         ioport->iop_papar       = PA_SP_MASK;
 512
 513         cpm->cp_pbdat           = PB_GP_OUTVAL;
 514         cpm->cp_pbodr           = PB_ODR_VAL;
 515         cpm->cp_pbdir           = PB_GP_OUTMASK | PB_SP_DIRVAL;
 516         cpm->cp_pbpar           = PB_SP_MASK;
 517
 518         ioport->iop_pcdat       = PC_GP_OUTVAL;
 519         ioport->iop_pcdir       = PC_GP_OUTMASK | PC_SP_DIRVAL;
 520         ioport->iop_pcso        = PC_SOVAL;
 521         ioport->iop_pcint       = PC_INTVAL;
 522         ioport->iop_pcpar       = PC_SP_MASK;
 523
 524         ioport->iop_pddat       = PD_GP_OUTVAL;
 525         ioport->iop_pddir       = PD_GP_OUTMASK | PD_SP_DIRVAL;
 526         ioport->iop_pdpar       = PD_SP_MASK;
 527
 528         ioport->iop_pddat |=  (1 << (15 - 6)) | (1 << (15 - 7));
 529
 530         return 0;
 531 }
 532
 533 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 534
 535 #include <linux/mtd/nand.h>
 536
 537 extern ulong nand_probe(ulong physadr);
 538 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 539
 540 void nand_init(void)
 541 {
 542         unsigned long totlen = nand_probe(CFG_NAND_BASE);
 543
 544         printf ("%4lu MB\n", totlen >> 20);
 545 }
 546 #endif
 547
 548 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
 549
 550 int pcmcia_init(void)
 551 {
 552         return 0;
 553 }
 554
 555 #endif
 556
 557 #ifdef CONFIG_POST
 558 /*
 559  * Returns 1 if keys pressed to start the power-on long-running tests
 560  * Called from board_init_f().
 561  */
 562 int post_hotkeys_pressed(void)
 563 {
 564         return 0;       /* No hotkeys supported */
 565 }
 566 #endif
 567
 568 #ifdef CONFIG_HW_WATCHDOG
 569
 570 void hw_watchdog_reset(void)
 571 {
 572         /* XXX add here the really funky stuff */
 573 }
 574
 575 #endif