board/pcs440ep/init.S

   1 /*
   2  * (C) Copyright 2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <ppc_asm.tmpl>
  25 #include <config.h>
  26
  27 /* General */
  28 #define TLB_VALID   0x00000200
  29
  30 /* Supported page sizes */
  31
  32 #define SZ_1K       0x00000000
  33 #define SZ_4K       0x00000010
  34 #define SZ_16K      0x00000020
  35 #define SZ_64K      0x00000030
  36 #define SZ_256K     0x00000040
  37 #define SZ_1M       0x00000050
  38 #define SZ_8M       0x00000060
  39 #define SZ_16M      0x00000070
  40 #define SZ_256M     0x00000090
  41
  42 /* Storage attributes */
  43 #define SA_W        0x00000800      /* Write-through */
  44 #define SA_I        0x00000400      /* Caching inhibited */
  45 #define SA_M        0x00000200      /* Memory coherence */
  46 #define SA_G        0x00000100      /* Guarded */
  47 #define SA_E        0x00000080      /* Endian */
  48
  49 /* Access control */
  50 #define AC_X        0x00000024      /* Execute */
  51 #define AC_W        0x00000012      /* Write */
  52 #define AC_R        0x00000009      /* Read */
  53
  54 /* Some handy macros */
  55
  56 #define EPN(e)          ((e) & 0xfffffc00)
  57 #define TLB0(epn,sz)    ( (EPN((epn)) | (sz) | TLB_VALID ) )
  58 #define TLB1(rpn,erpn)  ( ((rpn)&0xfffffc00) | (erpn) )
  59 #define TLB2(a)         ( (a)&0x00000fbf )
  60
  61 #define tlbtab_start\
  62         mflr    r1  ;\
  63         bl 0f       ;
  64
  65 #define tlbtab_end\
  66         .long 0, 0, 0   ;   \
  67 0:      mflr    r0      ;   \
  68         mtlr    r1      ;   \
  69         blr             ;
  70
  71 #define tlbentry(epn,sz,rpn,erpn,attr)\
  72         .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
  73
  74
  75 /**************************************************************************
  76  * TLB TABLE
  77  *
  78  * This table is used by the cpu boot code to setup the initial tlb
  79  * entries. Rather than make broad assumptions in the cpu source tree,
  80  * this table lets each board set things up however they like.
  81  *
  82  *  Pointer to the table is returned in r1
  83  *
  84  *************************************************************************/
  85
  86     .section .bootpg,"ax"
  87     .globl tlbtab
  88
  89 tlbtab:
  90         tlbtab_start
  91
  92         /*
  93          * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
  94          * speed up boot process. It is patched after relocation to enable SA_I
  95          */
  96         tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
  97
  98         /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
  99         tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
 100
 101         /*
 102          * TLB entries for SDRAM are not needed on this platform.
 103          * They are dynamically generated in the SPD DDR detection
 104          * routine.
 105          */
 106
 107         tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
 108
 109         /* PCI */
 110         tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
 111         tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
 112         tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
 113         tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
 114
 115         /* USB 2.0 Device */
 116         tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
 117
 118         tlbtab_end