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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / board / pm828 / pm828.c
1 /*
2 * (C) Copyright 2001-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <ioports.h>
26 #include <mpc8260.h>
27 #include <pci.h>
28 #include <netdev.h>
29
30 /*
31 * I/O Port configuration table
32 *
33 * if conf is 1, then that port pin will be configured at boot time
34 * according to the five values podr/pdir/ppar/psor/pdat for that entry
35 */
36
37 const iop_conf_t iop_conf_tab[4][32] = {
38
39 /* Port A configuration */
40 { /* conf ppar psor pdir podr pdat */
41 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
42 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
43 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
44 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
45 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
46 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
47 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */
48 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
49 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
50 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */
51 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
52 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
53 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
54 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
55 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
56 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/
57 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
58 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
59 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */
60 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */
61 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */
62 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */
63 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */
64 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */
65 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
66 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
67 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
68 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
69 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
70 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
71 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
72 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
73 },
74
75 /* Port B configuration */
76 { /* conf ppar psor pdir podr pdat */
77 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */
78 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */
79 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */
80 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
81 #ifdef CONFIG_ETHER_ON_FCC2
82 #error "SCC1 conflicts with FCC2"
83 #endif
84 /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
85 #else
86 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */
87 #endif
88 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */
89 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */
90 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */
91 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */
92 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */
93 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */
94 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */
95 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */
96 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */
97 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */
98 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
99 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
100 /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
101 /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
102 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
103 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
104 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
105 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
106 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
107 /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */
108 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
109 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
110 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
111 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
112 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
113 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
114 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
115 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
116 },
117
118 /* Port C */
119 { /* conf ppar psor pdir podr pdat */
120 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
121 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
122 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */
123 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */
124 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
125 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
126 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
127 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
128 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */
129 /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */
130 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */
131 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */
132 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */
133 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */
134 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
135 /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
136 /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
137 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */
138 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
139 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */
140 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */
141 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */
142 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */
143 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */
144 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
145 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
146 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
147 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
148 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
149 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */
150 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */
151 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */
152 },
153
154 /* Port D */
155 { /* conf ppar psor pdir podr pdat */
156 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
157 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */
158 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
159 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
160 /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
161 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
162 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
163 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
164 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */
165 /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */
166 /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */
167 /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */
168 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
169 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
170 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */
171 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */
172 #if defined(CONFIG_SOFT_I2C)
173 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
174 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
175 #else
176 #if defined(CONFIG_HARD_I2C)
177 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
178 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
179 #else /* normal I/O port pins */
180 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
181 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
182 #endif
183 #endif
184 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
185 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
186 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
187 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
188 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */
189 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */
190 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
191 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
192 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
193 /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
194 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
195 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
196 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
197 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
198 }
199 };
200
201 /* ------------------------------------------------------------------------- */
202
203 /* Check Board Identity:
204 */
205 int checkboard (void)
206 {
207 puts ("Board: PM828\n");
208 return 0;
209 }
210
211 /* ------------------------------------------------------------------------- */
212
213
214 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
215 *
216 * This routine performs standard 8260 initialization sequence
217 * and calculates the available memory size. It may be called
218 * several times to try different SDRAM configurations on both
219 * 60x and local buses.
220 */
221 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
222 ulong orx, volatile uchar * base)
223 {
224 volatile uchar c = 0xff;
225 volatile ulong cnt, val;
226 volatile ulong *addr;
227 volatile uint *sdmr_ptr;
228 volatile uint *orx_ptr;
229 int i;
230 ulong save[32]; /* to make test non-destructive */
231 ulong maxsize;
232
233 /* We must be able to test a location outsize the maximum legal size
234 * to find out THAT we are outside; but this address still has to be
235 * mapped by the controller. That means, that the initial mapping has
236 * to be (at least) twice as large as the maximum expected size.
237 */
238 maxsize = (1 + (~orx | 0x7fff)) / 2;
239
240 sdmr_ptr = &memctl->memc_psdmr;
241 orx_ptr = &memctl->memc_or2;
242
243 *orx_ptr = orx;
244
245 /*
246 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
247 *
248 * "At system reset, initialization software must set up the
249 * programmable parameters in the memory controller banks registers
250 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
251 * system software should execute the following initialization sequence
252 * for each SDRAM device.
253 *
254 * 1. Issue a PRECHARGE-ALL-BANKS command
255 * 2. Issue eight CBR REFRESH commands
256 * 3. Issue a MODE-SET command to initialize the mode register
257 *
258 * The initial commands are executed by setting P/LSDMR[OP] and
259 * accessing the SDRAM with a single-byte transaction."
260 *
261 * The appropriate BRx/ORx registers have already been set when we
262 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
263 */
264
265 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
266 *base = c;
267
268 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
269 for (i = 0; i < 8; i++)
270 *base = c;
271
272 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
273 *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
274
275 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
276 *base = c;
277
278 /*
279 * Check memory range for valid RAM. A simple memory test determines
280 * the actually available RAM size between addresses `base' and
281 * `base + maxsize'. Some (not all) hardware errors are detected:
282 * - short between address lines
283 * - short between data lines
284 */
285 i = 0;
286 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
287 addr = (volatile ulong *) base + cnt; /* pointer arith! */
288 save[i++] = *addr;
289 *addr = ~cnt;
290 }
291
292 addr = (volatile ulong *) base;
293 save[i] = *addr;
294 *addr = 0;
295
296 if ((val = *addr) != 0) {
297 *addr = save[i];
298 return (0);
299 }
300
301 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
302 addr = (volatile ulong *) base + cnt; /* pointer arith! */
303 val = *addr;
304 *addr = save[--i];
305 if (val != ~cnt) {
306 /* Write the actual size to ORx
307 */
308 *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
309 return (cnt * sizeof (long));
310 }
311 }
312 return (maxsize);
313 }
314
315
316 phys_size_t initdram (int board_type)
317 {
318 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
319 volatile memctl8260_t *memctl = &immap->im_memctl;
320
321 #ifndef CONFIG_SYS_RAMBOOT
322 ulong size8, size9;
323 #endif
324 ulong psize = 32 * 1024 * 1024;
325
326 memctl->memc_psrt = CONFIG_SYS_PSRT;
327 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
328
329 #ifndef CONFIG_SYS_RAMBOOT
330 size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
331 (uchar *) CONFIG_SYS_SDRAM_BASE);
332 size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
333 (uchar *) CONFIG_SYS_SDRAM_BASE);
334
335 if (size8 < size9) {
336 psize = size9;
337 printf ("(60x:9COL) ");
338 } else {
339 psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
340 (uchar *) CONFIG_SYS_SDRAM_BASE);
341 printf ("(60x:8COL) ");
342 }
343 #endif
344 return (psize);
345 }
346
347 #if defined(CONFIG_CMD_DOC)
348 void doc_init (void)
349 {
350 doc_probe (CONFIG_SYS_DOC_BASE);
351 }
352 #endif
353
354 #ifdef CONFIG_PCI
355 struct pci_controller hose;
356
357 extern void pci_mpc8250_init(struct pci_controller *);
358
359 void pci_init_board(void)
360 {
361 pci_mpc8250_init(&hose);
362 }
363 #endif
364
365 int board_eth_init(bd_t *bis)
366 {
367 return pci_eth_init(bis);
368 }