board/pm828/pm828.c

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <ioports.h>
  26 #include <mpc8260.h>
  27 #include <pci.h>
  28
  29 /*
  30  * I/O Port configuration table
  31  *
  32  * if conf is 1, then that port pin will be configured at boot time
  33  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  34  */
  35
  36 const iop_conf_t iop_conf_tab[4][32] = {
  37
  38     /* Port A configuration */
  39     {   /*            conf ppar psor pdir podr pdat */
  40         /* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 COL */
  41         /* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 CRS */
  42         /* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXER */
  43         /* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXEN */
  44         /* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXDV */
  45         /* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXER */
  46         /* PA25 */ {   0,   0,   0,   1,   0,   0   }, /* PA25 */
  47         /* PA24 */ {   0,   0,   0,   1,   0,   0   }, /* PA24 */
  48         /* PA23 */ {   0,   0,   0,   1,   0,   0   }, /* PA23 */
  49         /* PA22 */ {   0,   0,   0,   1,   0,   0   }, /* PA22 */
  50         /* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD3 */
  51         /* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD2 */
  52         /* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD1 */
  53         /* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD0 */
  54         /* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD0 */
  55         /* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD1*/
  56         /* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD2 */
  57         /* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD3 */
  58         /* PA13 */ {   0,   0,   0,   1,   0,   0   }, /* PA13 */
  59         /* PA12 */ {   0,   0,   0,   1,   0,   0   }, /* PA12 */
  60         /* PA11 */ {   0,   0,   0,   1,   0,   0   }, /* PA11 */
  61         /* PA10 */ {   0,   0,   0,   1,   0,   0   }, /* PA10 */
  62         /* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* PA9 */
  63         /* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* PA8 */
  64         /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  65         /* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
  66         /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  67         /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  68         /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  69         /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  70         /* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
  71         /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  72     },
  73
  74     /* Port B configuration */
  75     {   /*            conf ppar psor pdir podr pdat */
  76         /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TX_ER */
  77         /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_DV  */
  78         /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 TX_EN  */
  79 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
  80 #ifdef CONFIG_ETHER_ON_FCC2
  81 #error "SCC1 conflicts with FCC2"
  82 #endif
  83         /* PB28 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
  84 #else
  85         /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_ER */
  86 #endif
  87         /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 COL */
  88         /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 CRS */
  89         /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[3] */
  90         /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[2] */
  91         /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[1] */
  92         /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[0] */
  93         /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[0] */
  94         /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[1] */
  95         /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[2] */
  96         /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[3] */
  97         /* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
  98         /* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
  99         /* PB15 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
 100         /* PB14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC3 RXD */
 101         /* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
 102         /* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
 103         /* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
 104         /* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
 105         /* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
 106         /* PB8  */ {   1,   1,   1,   1,   0,   0   }, /* SCC3 TXD */
 107         /* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
 108         /* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
 109         /* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
 110         /* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
 111         /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 112         /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 113         /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 114         /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 115     },
 116
 117     /* Port C */
 118     {   /*            conf ppar psor pdir podr pdat */
 119         /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 120         /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 121         /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 CTS */
 122         /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* SCC2 CTS */
 123         /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* PC27 */
 124         /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 125         /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 126         /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 127         /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* PC23 */
 128         /* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK */
 129         /* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXCK */
 130         /* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK(2) */
 131         /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RXCK */
 132         /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 TXCK */
 133         /* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 134         /* PC16 */ {   0,   0,   0,   1,   0,   0   }, /* PC16 */
 135         /* PC15 */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
 136         /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 DCD */
 137         /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 138         /* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* SCC2 DCD */
 139         /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 CTS */
 140         /* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 DCD */
 141         /* PC9  */ {   0,   0,   0,   1,   0,   0   }, /* SCC4 CTS */
 142         /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* SCC4 DCD */
 143         /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 144         /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 145         /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 146         /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 147         /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 148         /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* PC2 */
 149         /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* PC1 */
 150         /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* PC0 */
 151     },
 152
 153     /* Port D */
 154     {   /*            conf ppar psor pdir podr pdat */
 155         /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
 156         /* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* PD30 */
 157         /* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
 158         /* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
 159         /* PD27 */ {   0,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
 160         /* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
 161         /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 162         /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 163         /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 RTS */
 164         /* PD22 */ {   1,   1,   0,   0,   0,   0   }, /* SCC4 RXD */
 165         /* PD21 */ {   1,   1,   0,   1,   0,   0   }, /* SCC4 TXD */
 166         /* PD20 */ {   0,   0,   1,   1,   0,   0   }, /* SCC4 RTS */
 167         /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 168         /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
 169         /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* PD17 */
 170         /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* PD16 */
 171 #if defined(CONFIG_SOFT_I2C)
 172         /* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
 173         /* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
 174 #else
 175 #if defined(CONFIG_HARD_I2C)
 176         /* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
 177         /* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
 178 #else /* normal I/O port pins */
 179         /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
 180         /* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
 181 #endif
 182 #endif
 183         /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 184         /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 185         /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 186         /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 187         /* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* PD9 */
 188         /* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* PD8 */
 189         /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 190         /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 191         /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 192         /* PD4  */ {   1,   1,   1,   0,   0,   0   }, /* SMC2 RXD */
 193         /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 194         /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 195         /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 196         /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 197     }
 198 };
 199
 200 /* ------------------------------------------------------------------------- */
 201
 202 /* Check Board Identity:
 203  */
 204 int checkboard (void)
 205 {
 206         puts ("Board: PM828\n");
 207         return 0;
 208 }
 209
 210 /* ------------------------------------------------------------------------- */
 211
 212
 213 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 214  *
 215  * This routine performs standard 8260 initialization sequence
 216  * and calculates the available memory size. It may be called
 217  * several times to try different SDRAM configurations on both
 218  * 60x and local buses.
 219  */
 220 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 221                                                   ulong orx, volatile uchar * base)
 222 {
 223         volatile uchar c = 0xff;
 224         volatile ulong cnt, val;
 225         volatile ulong *addr;
 226         volatile uint *sdmr_ptr;
 227         volatile uint *orx_ptr;
 228         int i;
 229         ulong save[32];                         /* to make test non-destructive */
 230         ulong maxsize;
 231
 232         /* We must be able to test a location outsize the maximum legal size
 233          * to find out THAT we are outside; but this address still has to be
 234          * mapped by the controller. That means, that the initial mapping has
 235          * to be (at least) twice as large as the maximum expected size.
 236          */
 237         maxsize = (1 + (~orx | 0x7fff)) / 2;
 238
 239         sdmr_ptr = &memctl->memc_psdmr;
 240         orx_ptr = &memctl->memc_or2;
 241
 242         *orx_ptr = orx;
 243
 244         /*
 245          * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 246          *
 247          * "At system reset, initialization software must set up the
 248          *  programmable parameters in the memory controller banks registers
 249          *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
 250          *  system software should execute the following initialization sequence
 251          *  for each SDRAM device.
 252          *
 253          *  1. Issue a PRECHARGE-ALL-BANKS command
 254          *  2. Issue eight CBR REFRESH commands
 255          *  3. Issue a MODE-SET command to initialize the mode register
 256          *
 257          *  The initial commands are executed by setting P/LSDMR[OP] and
 258          *  accessing the SDRAM with a single-byte transaction."
 259          *
 260          * The appropriate BRx/ORx registers have already been set when we
 261          * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
 262          */
 263
 264         *sdmr_ptr = sdmr | PSDMR_OP_PREA;
 265         *base = c;
 266
 267         *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
 268         for (i = 0; i < 8; i++)
 269                 *base = c;
 270
 271         *sdmr_ptr = sdmr | PSDMR_OP_MRW;
 272         *(base + CFG_MRS_OFFS) = c;     /* setting MR on address lines */
 273
 274         *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 275         *base = c;
 276
 277         /*
 278          * Check memory range for valid RAM. A simple memory test determines
 279          * the actually available RAM size between addresses `base' and
 280          * `base + maxsize'. Some (not all) hardware errors are detected:
 281          * - short between address lines
 282          * - short between data lines
 283          */
 284         i = 0;
 285         for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
 286                 addr = (volatile ulong *) base + cnt;   /* pointer arith! */
 287                 save[i++] = *addr;
 288                 *addr = ~cnt;
 289         }
 290
 291         addr = (volatile ulong *) base;
 292         save[i] = *addr;
 293         *addr = 0;
 294
 295         if ((val = *addr) != 0) {
 296                 *addr = save[i];
 297                 return (0);
 298         }
 299
 300         for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
 301                 addr = (volatile ulong *) base + cnt;   /* pointer arith! */
 302                 val = *addr;
 303                 *addr = save[--i];
 304                 if (val != ~cnt) {
 305                         /* Write the actual size to ORx
 306                          */
 307                         *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
 308                         return (cnt * sizeof (long));
 309                 }
 310         }
 311         return (maxsize);
 312 }
 313
 314
 315 long int initdram (int board_type)
 316 {
 317         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 318         volatile memctl8260_t *memctl = &immap->im_memctl;
 319
 320 #ifndef CFG_RAMBOOT
 321         ulong size8, size9;
 322 #endif
 323         ulong psize = 32 * 1024 * 1024;
 324
 325         memctl->memc_psrt = CFG_PSRT;
 326         memctl->memc_mptpr = CFG_MPTPR;
 327
 328 #ifndef CFG_RAMBOOT
 329         size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
 330                                           (uchar *) CFG_SDRAM_BASE);
 331         size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
 332                                           (uchar *) CFG_SDRAM_BASE);
 333
 334         if (size8 < size9) {
 335                 psize = size9;
 336                 printf ("(60x:9COL) ");
 337         } else {
 338                 psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
 339                                                   (uchar *) CFG_SDRAM_BASE);
 340                 printf ("(60x:8COL) ");
 341         }
 342 #endif
 343         return (psize);
 344 }
 345
 346 #if defined(CONFIG_CMD_DOC)
 347 extern void doc_probe (ulong physadr);
 348 void doc_init (void)
 349 {
 350         doc_probe (CFG_DOC_BASE);
 351 }
 352 #endif
 353
 354 #ifdef  CONFIG_PCI
 355 struct pci_controller hose;
 356
 357 extern void pci_mpc8250_init(struct pci_controller *);
 358
 359 void pci_init_board(void)
 360 {
 361         pci_mpc8250_init(&hose);
 362 }
 363 #endif