board/pm854/pm854.c

   1  /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003, Motorola Inc.
   4  * Xianghua Xiao, (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27
  28 #include <common.h>
  29 #include <pci.h>
  30 #include <netdev.h>
  31 #include <asm/processor.h>
  32 #include <asm/mmu.h>
  33 #include <asm/immap_85xx.h>
  34 #include <asm/fsl_ddr_sdram.h>
  35 #include <spd_sdram.h>
  36
  37 #if defined(CONFIG_DDR_ECC)
  38 extern void ddr_enable_ecc(unsigned int dram_size);
  39 #endif
  40
  41 void local_bus_init(void);
  42 void sdram_init(void);
  43 long int fixed_sdram(void);
  44
  45
  46 int board_early_init_f (void)
  47 {
  48 #if defined(CONFIG_PCI)
  49     volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
  50
  51     pci->peer &= 0xffffffdf; /* disable master abort */
  52 #endif
  53
  54     return 0;
  55 }
  56
  57 int checkboard (void)
  58 {
  59         puts("Board: MicroSys PM854\n");
  60
  61 #ifdef CONFIG_PCI
  62         printf("    PCI1: 32 bit, %d MHz (compiled)\n",
  63                CONFIG_SYS_CLK_FREQ / 1000000);
  64 #else
  65         printf("    PCI1: disabled\n");
  66 #endif
  67
  68         /*
  69          * Initialize local bus.
  70          */
  71         local_bus_init();
  72
  73         return 0;
  74 }
  75
  76
  77 phys_size_t
  78 initdram(int board_type)
  79 {
  80         long dram_size = 0;
  81
  82         puts("Initializing\n");
  83
  84 #if defined(CONFIG_DDR_DLL)
  85         {
  86             volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  87             int i,x;
  88
  89             x = 10;
  90
  91             /*
  92              * Work around to stabilize DDR DLL
  93              */
  94             gur->ddrdllcr = 0x81000000;
  95             asm("sync;isync;msync");
  96             udelay (200);
  97             while (gur->ddrdllcr != 0x81000100)
  98             {
  99                 gur->devdisr = gur->devdisr | 0x00010000;
 100                 asm("sync;isync;msync");
 101                 for (i=0; i<x; i++)
 102                     ;
 103                 gur->devdisr = gur->devdisr & 0xfff7ffff;
 104                 asm("sync;isync;msync");
 105                 x++;
 106             }
 107         }
 108 #endif
 109
 110 #if defined(CONFIG_SPD_EEPROM)
 111         dram_size = fsl_ddr_sdram();
 112         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 113         dram_size *= 0x100000;
 114 #else
 115         dram_size = fixed_sdram ();
 116 #endif
 117
 118 #if defined(CONFIG_DDR_ECC)
 119         /*
 120          * Initialize and enable DDR ECC.
 121          */
 122         ddr_enable_ecc(dram_size);
 123 #endif
 124         puts("    DDR: ");
 125         return dram_size;
 126 }
 127
 128
 129 /*
 130  * Initialize Local Bus
 131  */
 132
 133 void
 134 local_bus_init(void)
 135 {
 136         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 137         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 138
 139         uint clkdiv;
 140         uint lbc_hz;
 141         sys_info_t sysinfo;
 142
 143         /*
 144          * Errata LBC11.
 145          * Fix Local Bus clock glitch when DLL is enabled.
 146          *
 147          * If localbus freq is < 66Mhz, DLL bypass mode must be used.
 148          * If localbus freq is > 133Mhz, DLL can be safely enabled.
 149          * Between 66 and 133, the DLL is enabled with an override workaround.
 150          */
 151
 152         get_sys_info(&sysinfo);
 153         clkdiv = lbc->lcrr & 0x0f;
 154         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 155
 156         if (lbc_hz < 66) {
 157                 lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;   /* DLL Bypass */
 158
 159         } else if (lbc_hz >= 133) {
 160                 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 161
 162         } else {
 163                 /*
 164                  * On REV1 boards, need to change CLKDIV before enable DLL.
 165                  * Default CLKDIV is 8, change it to 4 temporarily.
 166                  */
 167                 uint pvr = get_pvr();
 168                 uint temp_lbcdll = 0;
 169
 170                 if (pvr == PVR_85xx_REV1) {
 171                         /* FIXME: Justify the high bit here. */
 172                         lbc->lcrr = 0x10000004;
 173                 }
 174
 175                 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 176                 udelay(200);
 177
 178                 /*
 179                  * Sample LBC DLL ctrl reg, upshift it to set the
 180                  * override bits.
 181                  */
 182                 temp_lbcdll = gur->lbcdllcr;
 183                 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 184                 asm("sync;isync;msync");
 185         }
 186 }
 187
 188
 189 #if defined(CONFIG_SYS_DRAM_TEST)
 190 int testdram (void)
 191 {
 192         uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
 193         uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 194         uint *p;
 195
 196         printf("SDRAM test phase 1:\n");
 197         for (p = pstart; p < pend; p++)
 198                 *p = 0xaaaaaaaa;
 199
 200         for (p = pstart; p < pend; p++) {
 201                 if (*p != 0xaaaaaaaa) {
 202                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 203                         return 1;
 204                 }
 205         }
 206
 207         printf("SDRAM test phase 2:\n");
 208         for (p = pstart; p < pend; p++)
 209                 *p = 0x55555555;
 210
 211         for (p = pstart; p < pend; p++) {
 212                 if (*p != 0x55555555) {
 213                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 214                         return 1;
 215                 }
 216         }
 217
 218         printf("SDRAM test passed.\n");
 219         return 0;
 220 }
 221 #endif
 222
 223
 224 #if !defined(CONFIG_SPD_EEPROM)
 225 /*************************************************************************
 226  *  fixed sdram init -- doesn't use serial presence detect.
 227  ************************************************************************/
 228 long int fixed_sdram (void)
 229 {
 230   #ifndef CONFIG_SYS_RAMBOOT
 231         volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 232
 233         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 234         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 235         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 236         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 237         ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
 238         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 239     #if defined (CONFIG_DDR_ECC)
 240         ddr->err_disable = 0x0000000D;
 241         ddr->err_sbe = 0x00ff0000;
 242     #endif
 243         asm("sync;isync;msync");
 244         udelay(500);
 245     #if defined (CONFIG_DDR_ECC)
 246         /* Enable ECC checking */
 247         ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 248     #else
 249         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 250     #endif
 251         asm("sync; isync; msync");
 252         udelay(500);
 253   #endif
 254         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 255 }
 256 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 257
 258
 259 #if defined(CONFIG_PCI)
 260 /*
 261  * Initialize PCI Devices, report devices found.
 262  */
 263
 264 #ifndef CONFIG_PCI_PNP
 265 static struct pci_config_table pci_pm854_config_table[] = {
 266     { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 267       PCI_IDSEL_NUMBER, PCI_ANY_ID,
 268       pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 269                                    PCI_ENET0_MEMADDR,
 270                                    PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
 271       } },
 272     { }
 273 };
 274 #endif
 275
 276
 277 static struct pci_controller hose = {
 278 #ifndef CONFIG_PCI_PNP
 279         config_table: pci_pm854_config_table,
 280 #endif
 281 };
 282
 283 #endif  /* CONFIG_PCI */
 284
 285
 286 void
 287 pci_init_board(void)
 288 {
 289 #ifdef CONFIG_PCI
 290         pci_mpc85xx_init(&hose);
 291 #endif /* CONFIG_PCI */
 292 }
 293
 294 int board_eth_init(bd_t *bis)
 295 {
 296         cpu_eth_init(bis);      /* Intialize TSECs first */
 297         return pci_eth_init(bis);
 298 }