board/prodrive/alpr/alpr.c

   1 /*
   2  * (C) Copyright 2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24
  25 #include <common.h>
  26 #include <asm/processor.h>
  27 #include <spd_sdram.h>
  28 #include <ppc4xx_enet.h>
  29 #include <miiphy.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 extern int alpr_fpga_init(void);
  34
  35 int board_early_init_f (void)
  36 {
  37         /*-------------------------------------------------------------------------
  38          * Initialize EBC CONFIG
  39          *-------------------------------------------------------------------------*/
  40         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
  41               EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
  42               EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
  43               EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
  44               EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
  45
  46         /*--------------------------------------------------------------------
  47          * Setup the interrupt controller polarities, triggers, etc.
  48          *-------------------------------------------------------------------*/
  49         mtdcr (uic0sr, 0xffffffff);     /* clear all */
  50         mtdcr (uic0er, 0x00000000);     /* disable all */
  51         mtdcr (uic0cr, 0x00000009);     /* SMI & UIC1 crit are critical */
  52         mtdcr (uic0pr, 0xfffffe03);     /* per manual */
  53         mtdcr (uic0tr, 0x01c00000);     /* per manual */
  54         mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
  55         mtdcr (uic0sr, 0xffffffff);     /* clear all */
  56
  57         mtdcr (uic1sr, 0xffffffff);     /* clear all */
  58         mtdcr (uic1er, 0x00000000);     /* disable all */
  59         mtdcr (uic1cr, 0x00000000);     /* all non-critical */
  60         mtdcr (uic1pr, 0xffffe0ff);     /* per ref-board manual */
  61         mtdcr (uic1tr, 0x00ffc000);     /* per ref-board manual */
  62         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
  63         mtdcr (uic1sr, 0xffffffff);     /* clear all */
  64
  65         mtdcr (uic2sr, 0xffffffff);     /* clear all */
  66         mtdcr (uic2er, 0x00000000);     /* disable all */
  67         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
  68         mtdcr (uic2pr, 0xffffffff);     /* per ref-board manual */
  69         mtdcr (uic2tr, 0x00ff8c0f);     /* per ref-board manual */
  70         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
  71         mtdcr (uic2sr, 0xffffffff);     /* clear all */
  72
  73         mtdcr (uicb0sr, 0xfc000000); /* clear all */
  74         mtdcr (uicb0er, 0x00000000); /* disable all */
  75         mtdcr (uicb0cr, 0x00000000); /* all non-critical */
  76         mtdcr (uicb0pr, 0xfc000000); /* */
  77         mtdcr (uicb0tr, 0x00000000); /* */
  78         mtdcr (uicb0vr, 0x00000001); /* */
  79
  80         /* Setup shutdown/SSD empty interrupt as inputs */
  81         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
  82         out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
  83
  84         /* Setup GPIO/IRQ multiplexing */
  85         mtsdr(sdr_pfc0, 0x01a33e00);
  86
  87         return 0;
  88 }
  89
  90 int last_stage_init(void)
  91 {
  92         unsigned short reg;
  93
  94         /*
  95          * Configure LED's of both Marvell 88E1111 PHY's
  96          *
  97          * This has to be done after the 4xx ethernet driver is loaded,
  98          * so "last_stage_init()" is the right place.
  99          */
 100         miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, &reg);
 101         reg |= 0x0001;
 102         miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
 103         miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, &reg);
 104         reg |= 0x0001;
 105         miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
 106
 107         return 0;
 108 }
 109
 110 static int board_rev(void)
 111 {
 112         /* Setup as input */
 113         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
 114         out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
 115
 116         return (in32(GPIO0_IR) >> 16) & 0x3;
 117 }
 118
 119 int checkboard (void)
 120 {
 121         char *s = getenv ("serial#");
 122
 123         printf ("Board: ALPR");
 124         if (s != NULL) {
 125                 puts (", serial# ");
 126                 puts (s);
 127         }
 128         printf(" (Rev. %d)\n", board_rev());
 129
 130         return (0);
 131 }
 132
 133 #if defined(CFG_DRAM_TEST)
 134 int testdram (void)
 135 {
 136         uint *pstart = (uint *) 0x00000000;
 137         uint *pend = (uint *) 0x08000000;
 138         uint *p;
 139
 140         for (p = pstart; p < pend; p++)
 141                 *p = 0xaaaaaaaa;
 142
 143         for (p = pstart; p < pend; p++) {
 144                 if (*p != 0xaaaaaaaa) {
 145                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 146                         return 1;
 147                 }
 148         }
 149
 150         for (p = pstart; p < pend; p++)
 151                 *p = 0x55555555;
 152
 153         for (p = pstart; p < pend; p++) {
 154                 if (*p != 0x55555555) {
 155                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 156                         return 1;
 157                 }
 158         }
 159         return 0;
 160 }
 161 #endif
 162
 163 /*************************************************************************
 164  *  pci_pre_init
 165  *
 166  *  This routine is called just prior to registering the hose and gives
 167  *  the board the opportunity to check things. Returning a value of zero
 168  *  indicates that things are bad & PCI initialization should be aborted.
 169  *
 170  *      Different boards may wish to customize the pci controller structure
 171  *      (add regions, override default access routines, etc) or perform
 172  *      certain pre-initialization actions.
 173  *
 174  ************************************************************************/
 175 #if defined(CONFIG_PCI)
 176 int pci_pre_init(struct pci_controller * hose )
 177 {
 178         unsigned long strap;
 179
 180         /*--------------------------------------------------------------------------+
 181          *      The ocotea board is always configured as the host & requires the
 182          *      PCI arbiter to be enabled.
 183          *--------------------------------------------------------------------------*/
 184         mfsdr(sdr_sdstp1, strap);
 185         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
 186                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 187                 return 0;
 188         }
 189
 190         /* FPGA Init */
 191         alpr_fpga_init ();
 192
 193         return 1;
 194 }
 195 #endif /* defined(CONFIG_PCI) */
 196
 197 /*************************************************************************
 198  *  pci_target_init
 199  *
 200  *      The bootstrap configuration provides default settings for the pci
 201  *      inbound map (PIM). But the bootstrap config choices are limited and
 202  *      may not be sufficient for a given board.
 203  *
 204  ************************************************************************/
 205 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 206 void pci_target_init(struct pci_controller * hose )
 207 {
 208         /*--------------------------------------------------------------------------+
 209          * Disable everything
 210          *--------------------------------------------------------------------------*/
 211         out32r( PCIX0_PIM0SA, 0 ); /* disable */
 212         out32r( PCIX0_PIM1SA, 0 ); /* disable */
 213         out32r( PCIX0_PIM2SA, 0 ); /* disable */
 214         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
 215
 216         /*--------------------------------------------------------------------------+
 217          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 218          * options to not support sizes such as 128/256 MB.
 219          *--------------------------------------------------------------------------*/
 220         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
 221         out32r( PCIX0_PIM0LAH, 0 );
 222         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 223
 224         out32r( PCIX0_BAR0, 0 );
 225
 226         /*--------------------------------------------------------------------------+
 227          * Program the board's subsystem id/vendor id
 228          *--------------------------------------------------------------------------*/
 229         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 230         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
 231
 232         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 233 }
 234 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 235
 236 /*************************************************************************
 237  *  is_pci_host
 238  *
 239  *      This routine is called to determine if a pci scan should be
 240  *      performed. With various hardware environments (especially cPCI and
 241  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 242  *      bit in the strap register, or generic host/adapter assumptions.
 243  *
 244  *      Rather than hard-code a bad assumption in the general 440 code, the
 245  *      440 pci code requires the board to decide at runtime.
 246  *
 247  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 248  *
 249  *
 250  ************************************************************************/
 251 #if defined(CONFIG_PCI)
 252
 253 static void wait_for_pci_ready(void)
 254 {
 255         /*
 256          * Configure EREADY as input
 257          */
 258         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY);
 259         udelay(1000);
 260
 261         for (;;) {
 262                 if (in32(GPIO0_IR) & CFG_GPIO_EREADY)
 263                         return;
 264         }
 265
 266 }
 267
 268 int is_pci_host(struct pci_controller *hose)
 269 {
 270         wait_for_pci_ready();
 271         return 1;               /* return 1 for host controller */
 272 }
 273 #endif /* defined(CONFIG_PCI) */
 274
 275 /*************************************************************************
 276  *  pci_master_init
 277  *
 278  ************************************************************************/
 279 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 280 void pci_master_init(struct pci_controller *hose)
 281 {
 282         /*--------------------------------------------------------------------------+
 283           | PowerPC440 PCI Master configuration.
 284           | Map PLB/processor addresses to PCI memory space.
 285           |   PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
 286           |   Use byte reversed out routines to handle endianess.
 287           | Make this region non-prefetchable.
 288           +--------------------------------------------------------------------------*/
 289         out32r( PCIX0_POM0SA, 0 ); /* disable */
 290         out32r( PCIX0_POM1SA, 0 ); /* disable */
 291         out32r( PCIX0_POM2SA, 0 ); /* disable */
 292
 293         out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */
 294         out32r(PCIX0_POM0LAH, 0x00000003);      /* PMM0 Local Address */
 295         out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 296         out32r(PCIX0_POM0PCIAH, 0x00000000);    /* PMM0 PCI High Address */
 297         out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1);    /* 256MB + enable region */
 298
 299         out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2);        /* PMM0 Local Address */
 300         out32r(PCIX0_POM1LAH, 0x00000003);      /* PMM0 Local Address */
 301         out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 302         out32r(PCIX0_POM1PCIAH, 0x00000000);    /* PMM0 PCI High Address */
 303         out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1);    /* 256MB + enable region */
 304 }
 305 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 306
 307 #ifdef CONFIG_POST
 308 /*
 309  * Returns 1 if keys pressed to start the power-on long-running tests
 310  * Called from board_init_f().
 311  */
 312 int post_hotkeys_pressed(void)
 313 {
 314
 315         return (ctrlc());
 316 }
 317 #endif