]>
git.ipfire.org Git - people/ms/u-boot.git/blob - board/prodrive/alpr/alpr.c
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <spd_sdram.h>
28 #include <ppc4xx_enet.h>
31 DECLARE_GLOBAL_DATA_PTR
;
33 extern int alpr_fpga_init(void);
35 int board_early_init_f (void)
37 /*-------------------------------------------------------------------------
38 * Initialize EBC CONFIG
39 *-------------------------------------------------------------------------*/
40 mtebc(xbcfg
, EBC_CFG_LE_UNLOCK
|
41 EBC_CFG_PTD_DISABLE
| EBC_CFG_RTC_64PERCLK
|
42 EBC_CFG_ATC_PREVIOUS
| EBC_CFG_DTC_PREVIOUS
|
43 EBC_CFG_CTC_PREVIOUS
| EBC_CFG_EMC_NONDEFAULT
|
44 EBC_CFG_PME_DISABLE
| EBC_CFG_PR_32
);
46 /*--------------------------------------------------------------------
47 * Setup the interrupt controller polarities, triggers, etc.
48 *-------------------------------------------------------------------*/
49 mtdcr (uic0sr
, 0xffffffff); /* clear all */
50 mtdcr (uic0er
, 0x00000000); /* disable all */
51 mtdcr (uic0cr
, 0x00000009); /* SMI & UIC1 crit are critical */
52 mtdcr (uic0pr
, 0xfffffe03); /* per manual */
53 mtdcr (uic0tr
, 0x01c00000); /* per manual */
54 mtdcr (uic0vr
, 0x00000001); /* int31 highest, base=0x000 */
55 mtdcr (uic0sr
, 0xffffffff); /* clear all */
57 mtdcr (uic1sr
, 0xffffffff); /* clear all */
58 mtdcr (uic1er
, 0x00000000); /* disable all */
59 mtdcr (uic1cr
, 0x00000000); /* all non-critical */
60 mtdcr (uic1pr
, 0xffffe0ff); /* per ref-board manual */
61 mtdcr (uic1tr
, 0x00ffc000); /* per ref-board manual */
62 mtdcr (uic1vr
, 0x00000001); /* int31 highest, base=0x000 */
63 mtdcr (uic1sr
, 0xffffffff); /* clear all */
65 mtdcr (uic2sr
, 0xffffffff); /* clear all */
66 mtdcr (uic2er
, 0x00000000); /* disable all */
67 mtdcr (uic2cr
, 0x00000000); /* all non-critical */
68 mtdcr (uic2pr
, 0xffffffff); /* per ref-board manual */
69 mtdcr (uic2tr
, 0x00ff8c0f); /* per ref-board manual */
70 mtdcr (uic2vr
, 0x00000001); /* int31 highest, base=0x000 */
71 mtdcr (uic2sr
, 0xffffffff); /* clear all */
73 mtdcr (uicb0sr
, 0xfc000000); /* clear all */
74 mtdcr (uicb0er
, 0x00000000); /* disable all */
75 mtdcr (uicb0cr
, 0x00000000); /* all non-critical */
76 mtdcr (uicb0pr
, 0xfc000000); /* */
77 mtdcr (uicb0tr
, 0x00000000); /* */
78 mtdcr (uicb0vr
, 0x00000001); /* */
80 /* Setup GPIO/IRQ multiplexing */
81 mtsdr(sdr_pfc0
, 0x01a03e00);
86 int last_stage_init(void)
91 * Configure LED's of both Marvell 88E1111 PHY's
93 * This has to be done after the 4xx ethernet driver is loaded,
94 * so "last_stage_init()" is the right place.
96 miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR
, 0x18, ®
);
98 miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR
, 0x18, reg
);
99 miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR
, 0x18, ®
);
101 miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR
, 0x18, reg
);
106 static int board_rev(void)
111 /* Setup GPIO14 & 15 as GPIO */
112 mfsdr(sdr_pfc0
, pfc0
);
113 pfc0
|= CFG_GPIO_REV0
| CFG_GPIO_REV1
;
114 mtsdr(sdr_pfc0
, pfc0
);
117 out32(GPIO0_TCR
, in32(GPIO0_TCR
) & ~(CFG_GPIO_REV0
| CFG_GPIO_REV0
));
118 out32(GPIO0_ODR
, in32(GPIO0_ODR
) & ~(CFG_GPIO_REV0
| CFG_GPIO_REV0
));
120 rev
= (in32(GPIO0_IR
) >> 16) & 0x3;
122 /* Setup GPIO14 & 15 as non GPIO again */
123 mfsdr(sdr_pfc0
, pfc0
);
124 pfc0
&= ~(CFG_GPIO_REV0
| CFG_GPIO_REV1
);
125 mtsdr(sdr_pfc0
, pfc0
);
130 int checkboard (void)
132 char *s
= getenv ("serial#");
134 printf ("Board: ALPR");
139 printf(" (Rev. %d)\n", board_rev());
144 #if defined(CFG_DRAM_TEST)
147 uint
*pstart
= (uint
*) 0x00000000;
148 uint
*pend
= (uint
*) 0x08000000;
151 for (p
= pstart
; p
< pend
; p
++)
154 for (p
= pstart
; p
< pend
; p
++) {
155 if (*p
!= 0xaaaaaaaa) {
156 printf ("SDRAM test fails at: %08x\n", (uint
) p
);
161 for (p
= pstart
; p
< pend
; p
++)
164 for (p
= pstart
; p
< pend
; p
++) {
165 if (*p
!= 0x55555555) {
166 printf ("SDRAM test fails at: %08x\n", (uint
) p
);
174 /*************************************************************************
177 * This routine is called just prior to registering the hose and gives
178 * the board the opportunity to check things. Returning a value of zero
179 * indicates that things are bad & PCI initialization should be aborted.
181 * Different boards may wish to customize the pci controller structure
182 * (add regions, override default access routines, etc) or perform
183 * certain pre-initialization actions.
185 ************************************************************************/
186 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
187 int pci_pre_init(struct pci_controller
* hose
)
191 /*--------------------------------------------------------------------------+
192 * The ocotea board is always configured as the host & requires the
193 * PCI arbiter to be enabled.
194 *--------------------------------------------------------------------------*/
195 mfsdr(sdr_sdstp1
, strap
);
196 if( (strap
& SDR0_SDSTP1_PAE_MASK
) == 0 ){
197 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap
);
206 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
208 /*************************************************************************
211 * The bootstrap configuration provides default settings for the pci
212 * inbound map (PIM). But the bootstrap config choices are limited and
213 * may not be sufficient for a given board.
215 ************************************************************************/
216 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
217 void pci_target_init(struct pci_controller
* hose
)
219 /*--------------------------------------------------------------------------+
221 *--------------------------------------------------------------------------*/
222 out32r( PCIX0_PIM0SA
, 0 ); /* disable */
223 out32r( PCIX0_PIM1SA
, 0 ); /* disable */
224 out32r( PCIX0_PIM2SA
, 0 ); /* disable */
225 out32r( PCIX0_EROMBA
, 0 ); /* disable expansion rom */
227 /*--------------------------------------------------------------------------+
228 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
229 * options to not support sizes such as 128/256 MB.
230 *--------------------------------------------------------------------------*/
231 out32r( PCIX0_PIM0LAL
, CFG_SDRAM_BASE
);
232 out32r( PCIX0_PIM0LAH
, 0 );
233 out32r( PCIX0_PIM0SA
, ~(gd
->ram_size
- 1) | 1 );
235 out32r( PCIX0_BAR0
, 0 );
237 /*--------------------------------------------------------------------------+
238 * Program the board's subsystem id/vendor id
239 *--------------------------------------------------------------------------*/
240 out16r( PCIX0_SBSYSVID
, CFG_PCI_SUBSYS_VENDORID
);
241 out16r( PCIX0_SBSYSID
, CFG_PCI_SUBSYS_DEVICEID
);
243 out16r( PCIX0_CMD
, in16r(PCIX0_CMD
) | PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
245 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
247 /*************************************************************************
250 * This routine is called to determine if a pci scan should be
251 * performed. With various hardware environments (especially cPCI and
252 * PPMC) it's insufficient to depend on the state of the arbiter enable
253 * bit in the strap register, or generic host/adapter assumptions.
255 * Rather than hard-code a bad assumption in the general 440 code, the
256 * 440 pci code requires the board to decide at runtime.
258 * Return 0 for adapter mode, non-zero for host (monarch) mode.
261 ************************************************************************/
262 #if defined(CONFIG_PCI)
264 static void wait_for_pci_ready(void)
267 * Configure EREADY as input
269 out32(GPIO0_TCR
, in32(GPIO0_TCR
) & ~CFG_GPIO_EREADY
);
273 if (in32(GPIO0_IR
) & CFG_GPIO_EREADY
)
279 int is_pci_host(struct pci_controller
*hose
)
281 wait_for_pci_ready();
282 return 1; /* return 1 for host controller */
284 #endif /* defined(CONFIG_PCI) */
286 /*************************************************************************
289 ************************************************************************/
290 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
291 void pci_master_init(struct pci_controller
*hose
)
293 /*--------------------------------------------------------------------------+
294 | PowerPC440 PCI Master configuration.
295 | Map PLB/processor addresses to PCI memory space.
296 | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
297 | Use byte reversed out routines to handle endianess.
298 | Make this region non-prefetchable.
299 +--------------------------------------------------------------------------*/
300 out32r( PCIX0_POM0SA
, 0 ); /* disable */
301 out32r( PCIX0_POM1SA
, 0 ); /* disable */
302 out32r( PCIX0_POM2SA
, 0 ); /* disable */
304 out32r(PCIX0_POM0LAL
, CFG_PCI_MEMBASE
); /* PMM0 Local Address */
305 out32r(PCIX0_POM0LAH
, 0x00000003); /* PMM0 Local Address */
306 out32r(PCIX0_POM0PCIAL
, CFG_PCI_MEMBASE
); /* PMM0 PCI Low Address */
307 out32r(PCIX0_POM0PCIAH
, 0x00000000); /* PMM0 PCI High Address */
308 out32r(PCIX0_POM0SA
, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
310 out32r(PCIX0_POM1LAL
, CFG_PCI_MEMBASE2
); /* PMM0 Local Address */
311 out32r(PCIX0_POM1LAH
, 0x00000003); /* PMM0 Local Address */
312 out32r(PCIX0_POM1PCIAL
, CFG_PCI_MEMBASE2
); /* PMM0 PCI Low Address */
313 out32r(PCIX0_POM1PCIAH
, 0x00000000); /* PMM0 PCI High Address */
314 out32r(PCIX0_POM1SA
, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
316 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
320 * Returns 1 if keys pressed to start the power-on long-running tests
321 * Called from board_init_f().
323 int post_hotkeys_pressed(void)