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git.ipfire.org Git - people/ms/u-boot.git/blob - board/prodrive/alpr/alpr.c
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <fdt_support.h>
28 #include <spd_sdram.h>
29 #include <ppc4xx_enet.h>
31 #include <asm/processor.h>
33 DECLARE_GLOBAL_DATA_PTR
;
35 extern int alpr_fpga_init(void);
37 int board_early_init_f (void)
39 /*-------------------------------------------------------------------------
40 * Initialize EBC CONFIG
41 *-------------------------------------------------------------------------*/
42 mtebc(xbcfg
, EBC_CFG_LE_UNLOCK
|
43 EBC_CFG_PTD_DISABLE
| EBC_CFG_RTC_64PERCLK
|
44 EBC_CFG_ATC_PREVIOUS
| EBC_CFG_DTC_PREVIOUS
|
45 EBC_CFG_CTC_PREVIOUS
| EBC_CFG_EMC_NONDEFAULT
|
46 EBC_CFG_PME_DISABLE
| EBC_CFG_PR_32
);
48 /*--------------------------------------------------------------------
49 * Setup the interrupt controller polarities, triggers, etc.
50 *-------------------------------------------------------------------*/
52 * Because of the interrupt handling rework to handle 440GX interrupts
53 * with the common code, we needed to change names of the UIC registers.
54 * Here the new relationship:
56 * U-Boot name 440GX name
57 * -----------------------
63 mtdcr (uic1sr
, 0xffffffff); /* clear all */
64 mtdcr (uic1er
, 0x00000000); /* disable all */
65 mtdcr (uic1cr
, 0x00000009); /* SMI & UIC1 crit are critical */
66 mtdcr (uic1pr
, 0xfffffe03); /* per manual */
67 mtdcr (uic1tr
, 0x01c00000); /* per manual */
68 mtdcr (uic1vr
, 0x00000001); /* int31 highest, base=0x000 */
69 mtdcr (uic1sr
, 0xffffffff); /* clear all */
71 mtdcr (uic2sr
, 0xffffffff); /* clear all */
72 mtdcr (uic2er
, 0x00000000); /* disable all */
73 mtdcr (uic2cr
, 0x00000000); /* all non-critical */
74 mtdcr (uic2pr
, 0xffffe0ff); /* per ref-board manual */
75 mtdcr (uic2tr
, 0x00ffc000); /* per ref-board manual */
76 mtdcr (uic2vr
, 0x00000001); /* int31 highest, base=0x000 */
77 mtdcr (uic2sr
, 0xffffffff); /* clear all */
79 mtdcr (uic3sr
, 0xffffffff); /* clear all */
80 mtdcr (uic3er
, 0x00000000); /* disable all */
81 mtdcr (uic3cr
, 0x00000000); /* all non-critical */
82 mtdcr (uic3pr
, 0xffffffff); /* per ref-board manual */
83 mtdcr (uic3tr
, 0x00ff8c0f); /* per ref-board manual */
84 mtdcr (uic3vr
, 0x00000001); /* int31 highest, base=0x000 */
85 mtdcr (uic3sr
, 0xffffffff); /* clear all */
87 mtdcr (uic0sr
, 0xfc000000); /* clear all */
88 mtdcr (uic0er
, 0x00000000); /* disable all */
89 mtdcr (uic0cr
, 0x00000000); /* all non-critical */
90 mtdcr (uic0pr
, 0xfc000000); /* */
91 mtdcr (uic0tr
, 0x00000000); /* */
92 mtdcr (uic0vr
, 0x00000001); /* */
94 /* Setup shutdown/SSD empty interrupt as inputs */
95 out32(GPIO0_TCR
, in32(GPIO0_TCR
) & ~(CFG_GPIO_SHUTDOWN
| CFG_GPIO_SSD_EMPTY
));
96 out32(GPIO0_ODR
, in32(GPIO0_ODR
) & ~(CFG_GPIO_SHUTDOWN
| CFG_GPIO_SSD_EMPTY
));
98 /* Setup GPIO/IRQ multiplexing */
99 mtsdr(sdr_pfc0
, 0x01a33e00);
104 int last_stage_init(void)
109 * Configure LED's of both Marvell 88E1111 PHY's
111 * This has to be done after the 4xx ethernet driver is loaded,
112 * so "last_stage_init()" is the right place.
114 miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR
, 0x18, ®
);
116 miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR
, 0x18, reg
);
117 miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR
, 0x18, ®
);
119 miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR
, 0x18, reg
);
124 static int board_rev(void)
127 out32(GPIO0_TCR
, in32(GPIO0_TCR
) & ~(CFG_GPIO_REV0
| CFG_GPIO_REV1
));
128 out32(GPIO0_ODR
, in32(GPIO0_ODR
) & ~(CFG_GPIO_REV0
| CFG_GPIO_REV1
));
130 return (in32(GPIO0_IR
) >> 16) & 0x3;
133 int checkboard (void)
135 char *s
= getenv ("serial#");
137 printf ("Board: ALPR");
142 printf(" (Rev. %d)\n", board_rev());
147 /*************************************************************************
150 * This routine is called just prior to registering the hose and gives
151 * the board the opportunity to check things. Returning a value of zero
152 * indicates that things are bad & PCI initialization should be aborted.
154 * Different boards may wish to customize the pci controller structure
155 * (add regions, override default access routines, etc) or perform
156 * certain pre-initialization actions.
158 ************************************************************************/
159 #if defined(CONFIG_PCI)
160 int pci_pre_init(struct pci_controller
* hose
)
164 /*--------------------------------------------------------------------------+
165 * The ocotea board is always configured as the host & requires the
166 * PCI arbiter to be enabled.
167 *--------------------------------------------------------------------------*/
168 mfsdr(sdr_sdstp1
, strap
);
169 if( (strap
& SDR0_SDSTP1_PAE_MASK
) == 0 ){
170 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap
);
179 #endif /* defined(CONFIG_PCI) */
181 /*************************************************************************
184 * The bootstrap configuration provides default settings for the pci
185 * inbound map (PIM). But the bootstrap config choices are limited and
186 * may not be sufficient for a given board.
188 ************************************************************************/
189 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
190 void pci_target_init(struct pci_controller
* hose
)
192 /*--------------------------------------------------------------------------+
194 *--------------------------------------------------------------------------*/
195 out32r( PCIX0_PIM0SA
, 0 ); /* disable */
196 out32r( PCIX0_PIM1SA
, 0 ); /* disable */
197 out32r( PCIX0_PIM2SA
, 0 ); /* disable */
198 out32r( PCIX0_EROMBA
, 0 ); /* disable expansion rom */
200 /*--------------------------------------------------------------------------+
201 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
202 * options to not support sizes such as 128/256 MB.
203 *--------------------------------------------------------------------------*/
204 out32r( PCIX0_PIM0LAL
, CFG_SDRAM_BASE
);
205 out32r( PCIX0_PIM0LAH
, 0 );
206 out32r( PCIX0_PIM0SA
, ~(gd
->ram_size
- 1) | 1 );
208 out32r( PCIX0_BAR0
, 0 );
210 /*--------------------------------------------------------------------------+
211 * Program the board's subsystem id/vendor id
212 *--------------------------------------------------------------------------*/
213 out16r( PCIX0_SBSYSVID
, CFG_PCI_SUBSYS_VENDORID
);
214 out16r( PCIX0_SBSYSID
, CFG_PCI_SUBSYS_DEVICEID
);
216 out16r( PCIX0_CMD
, in16r(PCIX0_CMD
) | PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
218 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
220 /*************************************************************************
223 * This routine is called to determine if a pci scan should be
224 * performed. With various hardware environments (especially cPCI and
225 * PPMC) it's insufficient to depend on the state of the arbiter enable
226 * bit in the strap register, or generic host/adapter assumptions.
228 * Rather than hard-code a bad assumption in the general 440 code, the
229 * 440 pci code requires the board to decide at runtime.
231 * Return 0 for adapter mode, non-zero for host (monarch) mode.
234 ************************************************************************/
235 #if defined(CONFIG_PCI)
237 static void wait_for_pci_ready(void)
240 * Configure EREADY as input
242 out32(GPIO0_TCR
, in32(GPIO0_TCR
) & ~CFG_GPIO_EREADY
);
246 if (in32(GPIO0_IR
) & CFG_GPIO_EREADY
)
252 int is_pci_host(struct pci_controller
*hose
)
254 wait_for_pci_ready();
255 return 1; /* return 1 for host controller */
257 #endif /* defined(CONFIG_PCI) */
259 /*************************************************************************
262 ************************************************************************/
263 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
264 void pci_master_init(struct pci_controller
*hose
)
266 /*--------------------------------------------------------------------------+
267 | PowerPC440 PCI Master configuration.
268 | Map PLB/processor addresses to PCI memory space.
269 | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
270 | Use byte reversed out routines to handle endianess.
271 | Make this region non-prefetchable.
272 +--------------------------------------------------------------------------*/
273 out32r( PCIX0_POM0SA
, 0 ); /* disable */
274 out32r( PCIX0_POM1SA
, 0 ); /* disable */
275 out32r( PCIX0_POM2SA
, 0 ); /* disable */
277 out32r(PCIX0_POM0LAL
, CFG_PCI_MEMBASE
); /* PMM0 Local Address */
278 out32r(PCIX0_POM0LAH
, 0x00000003); /* PMM0 Local Address */
279 out32r(PCIX0_POM0PCIAL
, CFG_PCI_MEMBASE
); /* PMM0 PCI Low Address */
280 out32r(PCIX0_POM0PCIAH
, 0x00000000); /* PMM0 PCI High Address */
281 out32r(PCIX0_POM0SA
, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
283 out32r(PCIX0_POM1LAL
, CFG_PCI_MEMBASE2
); /* PMM0 Local Address */
284 out32r(PCIX0_POM1LAH
, 0x00000003); /* PMM0 Local Address */
285 out32r(PCIX0_POM1PCIAL
, CFG_PCI_MEMBASE2
); /* PMM0 PCI Low Address */
286 out32r(PCIX0_POM1PCIAH
, 0x00000000); /* PMM0 PCI High Address */
287 out32r(PCIX0_POM1SA
, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
289 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
293 * Returns 1 if keys pressed to start the power-on long-running tests
294 * Called from board_init_f().
296 int post_hotkeys_pressed(void)