board/prodrive/alpr/alpr.c

   1 /*
   2  * (C) Copyright 2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24
  25 #include <common.h>
  26 #include <asm/processor.h>
  27 #include <spd_sdram.h>
  28 #include <ppc4xx_enet.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 extern int alpr_fpga_init(void);
  33
  34 int board_early_init_f (void)
  35 {
  36         unsigned long mfr;
  37
  38         /*-------------------------------------------------------------------------+
  39           | Initialize EBC CONFIG
  40           +-------------------------------------------------------------------------*/
  41 #if 0
  42         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
  43               EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
  44               EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
  45               EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
  46               EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
  47 #else
  48         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
  49               EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
  50               EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
  51               EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
  52               EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
  53 #endif
  54
  55         /*--------------------------------------------------------------------
  56          * Setup the interrupt controller polarities, triggers, etc.
  57          *-------------------------------------------------------------------*/
  58         mtdcr (uic0sr, 0xffffffff);     /* clear all */
  59         mtdcr (uic0er, 0x00000000);     /* disable all */
  60         mtdcr (uic0cr, 0x00000009);     /* SMI & UIC1 crit are critical */
  61         mtdcr (uic0pr, 0xfffffe13);     /* per ref-board manual */
  62         mtdcr (uic0tr, 0x01c00008);     /* per ref-board manual */
  63         mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
  64         mtdcr (uic0sr, 0xffffffff);     /* clear all */
  65
  66         mtdcr (uic1sr, 0xffffffff);     /* clear all */
  67         mtdcr (uic1er, 0x00000000);     /* disable all */
  68         mtdcr (uic1cr, 0x00000000);     /* all non-critical */
  69         mtdcr (uic1pr, 0xffffe0ff);     /* per ref-board manual */
  70         mtdcr (uic1tr, 0x00ffc000);     /* per ref-board manual */
  71         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
  72         mtdcr (uic1sr, 0xffffffff);     /* clear all */
  73
  74         mtdcr (uic2sr, 0xffffffff);     /* clear all */
  75         mtdcr (uic2er, 0x00000000);     /* disable all */
  76         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
  77         mtdcr (uic2pr, 0xffffffff);     /* per ref-board manual */
  78         mtdcr (uic2tr, 0x00ff8c0f);     /* per ref-board manual */
  79         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
  80         mtdcr (uic2sr, 0xffffffff);     /* clear all */
  81
  82         mtdcr (uicb0sr, 0xfc000000); /* clear all */
  83         mtdcr (uicb0er, 0x00000000); /* disable all */
  84         mtdcr (uicb0cr, 0x00000000); /* all non-critical */
  85         mtdcr (uicb0pr, 0xfc000000); /* */
  86         mtdcr (uicb0tr, 0x00000000); /* */
  87         mtdcr (uicb0vr, 0x00000001); /* */
  88         mfsdr (sdr_mfr, mfr);
  89         mfr &= ~SDR0_MFR_ECS_MASK;
  90
  91         return 0;
  92 }
  93
  94 int checkboard (void)
  95 {
  96         char *s = getenv ("serial#");
  97
  98         printf ("Board: ALPR");
  99         if (s != NULL) {
 100                 puts (", serial# ");
 101                 puts (s);
 102         }
 103         putc ('\n');
 104
 105         return (0);
 106 }
 107
 108 #if defined(CFG_DRAM_TEST)
 109 int testdram (void)
 110 {
 111         uint *pstart = (uint *) 0x00000000;
 112         uint *pend = (uint *) 0x08000000;
 113         uint *p;
 114
 115         for (p = pstart; p < pend; p++)
 116                 *p = 0xaaaaaaaa;
 117
 118         for (p = pstart; p < pend; p++) {
 119                 if (*p != 0xaaaaaaaa) {
 120                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 121                         return 1;
 122                 }
 123         }
 124
 125         for (p = pstart; p < pend; p++)
 126                 *p = 0x55555555;
 127
 128         for (p = pstart; p < pend; p++) {
 129                 if (*p != 0x55555555) {
 130                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 131                         return 1;
 132                 }
 133         }
 134         return 0;
 135 }
 136 #endif
 137
 138 /*************************************************************************
 139  *  pci_pre_init
 140  *
 141  *  This routine is called just prior to registering the hose and gives
 142  *  the board the opportunity to check things. Returning a value of zero
 143  *  indicates that things are bad & PCI initialization should be aborted.
 144  *
 145  *      Different boards may wish to customize the pci controller structure
 146  *      (add regions, override default access routines, etc) or perform
 147  *      certain pre-initialization actions.
 148  *
 149  ************************************************************************/
 150 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 151 int pci_pre_init(struct pci_controller * hose )
 152 {
 153         unsigned long strap;
 154
 155         /*--------------------------------------------------------------------------+
 156          *      The ocotea board is always configured as the host & requires the
 157          *      PCI arbiter to be enabled.
 158          *--------------------------------------------------------------------------*/
 159         mfsdr(sdr_sdstp1, strap);
 160         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
 161                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 162                 return 0;
 163         }
 164
 165         /* FPGA Init */
 166         alpr_fpga_init ();
 167
 168         return 1;
 169 }
 170 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 171
 172 /*************************************************************************
 173  *  pci_target_init
 174  *
 175  *      The bootstrap configuration provides default settings for the pci
 176  *      inbound map (PIM). But the bootstrap config choices are limited and
 177  *      may not be sufficient for a given board.
 178  *
 179  ************************************************************************/
 180 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 181 void pci_target_init(struct pci_controller * hose )
 182 {
 183         /*--------------------------------------------------------------------------+
 184          * Disable everything
 185          *--------------------------------------------------------------------------*/
 186         out32r( PCIX0_PIM0SA, 0 ); /* disable */
 187         out32r( PCIX0_PIM1SA, 0 ); /* disable */
 188         out32r( PCIX0_PIM2SA, 0 ); /* disable */
 189         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
 190
 191         /*--------------------------------------------------------------------------+
 192          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 193          * options to not support sizes such as 128/256 MB.
 194          *--------------------------------------------------------------------------*/
 195         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
 196         out32r( PCIX0_PIM0LAH, 0 );
 197         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 198
 199         out32r( PCIX0_BAR0, 0 );
 200
 201         /*--------------------------------------------------------------------------+
 202          * Program the board's subsystem id/vendor id
 203          *--------------------------------------------------------------------------*/
 204         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 205         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
 206
 207         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 208 }
 209 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 210
 211 /*************************************************************************
 212  *  is_pci_host
 213  *
 214  *      This routine is called to determine if a pci scan should be
 215  *      performed. With various hardware environments (especially cPCI and
 216  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 217  *      bit in the strap register, or generic host/adapter assumptions.
 218  *
 219  *      Rather than hard-code a bad assumption in the general 440 code, the
 220  *      440 pci code requires the board to decide at runtime.
 221  *
 222  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 223  *
 224  *
 225  ************************************************************************/
 226 #if defined(CONFIG_PCI)
 227 int is_pci_host(struct pci_controller *hose)
 228 {
 229     /* The ocotea board is always configured as host. */
 230     return(1);
 231 }
 232 #endif /* defined(CONFIG_PCI) */
 233
 234 /*************************************************************************
 235  *  pci_master_init
 236  *
 237  ************************************************************************/
 238 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 239 void pci_master_init(struct pci_controller *hose)
 240 {
 241         /*--------------------------------------------------------------------------+
 242           | PowerPC440 PCI Master configuration.
 243           | Map PLB/processor addresses to PCI memory space.
 244           |   PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
 245           |   Use byte reversed out routines to handle endianess.
 246           | Make this region non-prefetchable.
 247           +--------------------------------------------------------------------------*/
 248         out32r( PCIX0_POM0SA, 0 ); /* disable */
 249         out32r( PCIX0_POM1SA, 0 ); /* disable */
 250         out32r( PCIX0_POM2SA, 0 ); /* disable */
 251
 252         out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */
 253         out32r(PCIX0_POM0LAH, 0x00000003);      /* PMM0 Local Address */
 254         out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 255         out32r(PCIX0_POM0PCIAH, 0x00000000);    /* PMM0 PCI High Address */
 256         out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1);    /* 256MB + enable region */
 257
 258         out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2);        /* PMM0 Local Address */
 259         out32r(PCIX0_POM1LAH, 0x00000003);      /* PMM0 Local Address */
 260         out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 261         out32r(PCIX0_POM1PCIAH, 0x00000000);    /* PMM0 PCI High Address */
 262         out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1);    /* 256MB + enable region */
 263 }
 264 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 265
 266 #ifdef CONFIG_POST
 267 /*
 268  * Returns 1 if keys pressed to start the power-on long-running tests
 269  * Called from board_init_f().
 270  */
 271 int post_hotkeys_pressed(void)
 272 {
 273
 274         return (ctrlc());
 275 }
 276 #endif
 277
 278 void board_reset(void)
 279 {
 280         /*
 281          * Initiate chip reset in debug control register DBCR
 282          */
 283         mtspr(dbcr0, 0x20000000);
 284 }