board/prodrive/alpr/alpr.c

   1 /*
   2  * (C) Copyright 2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24
  25 #include <common.h>
  26 #include <libfdt.h>
  27 #include <fdt_support.h>
  28 #include <spd_sdram.h>
  29 #include <ppc4xx_enet.h>
  30 #include <miiphy.h>
  31 #include <asm/processor.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 extern int alpr_fpga_init(void);
  36
  37 int board_early_init_f (void)
  38 {
  39         /*-------------------------------------------------------------------------
  40          * Initialize EBC CONFIG
  41          *-------------------------------------------------------------------------*/
  42         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
  43               EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
  44               EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
  45               EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
  46               EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
  47
  48         /*--------------------------------------------------------------------
  49          * Setup the interrupt controller polarities, triggers, etc.
  50          *-------------------------------------------------------------------*/
  51         mtdcr (uic0sr, 0xffffffff);     /* clear all */
  52         mtdcr (uic0er, 0x00000000);     /* disable all */
  53         mtdcr (uic0cr, 0x00000009);     /* SMI & UIC1 crit are critical */
  54         mtdcr (uic0pr, 0xfffffe03);     /* per manual */
  55         mtdcr (uic0tr, 0x01c00000);     /* per manual */
  56         mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
  57         mtdcr (uic0sr, 0xffffffff);     /* clear all */
  58
  59         mtdcr (uic1sr, 0xffffffff);     /* clear all */
  60         mtdcr (uic1er, 0x00000000);     /* disable all */
  61         mtdcr (uic1cr, 0x00000000);     /* all non-critical */
  62         mtdcr (uic1pr, 0xffffe0ff);     /* per ref-board manual */
  63         mtdcr (uic1tr, 0x00ffc000);     /* per ref-board manual */
  64         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
  65         mtdcr (uic1sr, 0xffffffff);     /* clear all */
  66
  67         mtdcr (uic2sr, 0xffffffff);     /* clear all */
  68         mtdcr (uic2er, 0x00000000);     /* disable all */
  69         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
  70         mtdcr (uic2pr, 0xffffffff);     /* per ref-board manual */
  71         mtdcr (uic2tr, 0x00ff8c0f);     /* per ref-board manual */
  72         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
  73         mtdcr (uic2sr, 0xffffffff);     /* clear all */
  74
  75         mtdcr (uicb0sr, 0xfc000000); /* clear all */
  76         mtdcr (uicb0er, 0x00000000); /* disable all */
  77         mtdcr (uicb0cr, 0x00000000); /* all non-critical */
  78         mtdcr (uicb0pr, 0xfc000000); /* */
  79         mtdcr (uicb0tr, 0x00000000); /* */
  80         mtdcr (uicb0vr, 0x00000001); /* */
  81
  82         /* Setup shutdown/SSD empty interrupt as inputs */
  83         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
  84         out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
  85
  86         /* Setup GPIO/IRQ multiplexing */
  87         mtsdr(sdr_pfc0, 0x01a33e00);
  88
  89         return 0;
  90 }
  91
  92 int last_stage_init(void)
  93 {
  94         unsigned short reg;
  95
  96         /*
  97          * Configure LED's of both Marvell 88E1111 PHY's
  98          *
  99          * This has to be done after the 4xx ethernet driver is loaded,
 100          * so "last_stage_init()" is the right place.
 101          */
 102         miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, &reg);
 103         reg |= 0x0001;
 104         miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
 105         miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, &reg);
 106         reg |= 0x0001;
 107         miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
 108
 109         return 0;
 110 }
 111
 112 static int board_rev(void)
 113 {
 114         /* Setup as input */
 115         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
 116         out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
 117
 118         return (in32(GPIO0_IR) >> 16) & 0x3;
 119 }
 120
 121 int checkboard (void)
 122 {
 123         char *s = getenv ("serial#");
 124
 125         printf ("Board: ALPR");
 126         if (s != NULL) {
 127                 puts (", serial# ");
 128                 puts (s);
 129         }
 130         printf(" (Rev. %d)\n", board_rev());
 131
 132         return (0);
 133 }
 134
 135 /*************************************************************************
 136  *  pci_pre_init
 137  *
 138  *  This routine is called just prior to registering the hose and gives
 139  *  the board the opportunity to check things. Returning a value of zero
 140  *  indicates that things are bad & PCI initialization should be aborted.
 141  *
 142  *      Different boards may wish to customize the pci controller structure
 143  *      (add regions, override default access routines, etc) or perform
 144  *      certain pre-initialization actions.
 145  *
 146  ************************************************************************/
 147 #if defined(CONFIG_PCI)
 148 int pci_pre_init(struct pci_controller * hose )
 149 {
 150         unsigned long strap;
 151
 152         /*--------------------------------------------------------------------------+
 153          *      The ocotea board is always configured as the host & requires the
 154          *      PCI arbiter to be enabled.
 155          *--------------------------------------------------------------------------*/
 156         mfsdr(sdr_sdstp1, strap);
 157         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
 158                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 159                 return 0;
 160         }
 161
 162         /* FPGA Init */
 163         alpr_fpga_init ();
 164
 165         return 1;
 166 }
 167 #endif /* defined(CONFIG_PCI) */
 168
 169 /*************************************************************************
 170  *  pci_target_init
 171  *
 172  *      The bootstrap configuration provides default settings for the pci
 173  *      inbound map (PIM). But the bootstrap config choices are limited and
 174  *      may not be sufficient for a given board.
 175  *
 176  ************************************************************************/
 177 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 178 void pci_target_init(struct pci_controller * hose )
 179 {
 180         /*--------------------------------------------------------------------------+
 181          * Disable everything
 182          *--------------------------------------------------------------------------*/
 183         out32r( PCIX0_PIM0SA, 0 ); /* disable */
 184         out32r( PCIX0_PIM1SA, 0 ); /* disable */
 185         out32r( PCIX0_PIM2SA, 0 ); /* disable */
 186         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
 187
 188         /*--------------------------------------------------------------------------+
 189          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 190          * options to not support sizes such as 128/256 MB.
 191          *--------------------------------------------------------------------------*/
 192         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
 193         out32r( PCIX0_PIM0LAH, 0 );
 194         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 195
 196         out32r( PCIX0_BAR0, 0 );
 197
 198         /*--------------------------------------------------------------------------+
 199          * Program the board's subsystem id/vendor id
 200          *--------------------------------------------------------------------------*/
 201         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 202         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
 203
 204         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 205 }
 206 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 207
 208 /*************************************************************************
 209  *  is_pci_host
 210  *
 211  *      This routine is called to determine if a pci scan should be
 212  *      performed. With various hardware environments (especially cPCI and
 213  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 214  *      bit in the strap register, or generic host/adapter assumptions.
 215  *
 216  *      Rather than hard-code a bad assumption in the general 440 code, the
 217  *      440 pci code requires the board to decide at runtime.
 218  *
 219  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 220  *
 221  *
 222  ************************************************************************/
 223 #if defined(CONFIG_PCI)
 224
 225 static void wait_for_pci_ready(void)
 226 {
 227         /*
 228          * Configure EREADY as input
 229          */
 230         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY);
 231         udelay(1000);
 232
 233         for (;;) {
 234                 if (in32(GPIO0_IR) & CFG_GPIO_EREADY)
 235                         return;
 236         }
 237
 238 }
 239
 240 int is_pci_host(struct pci_controller *hose)
 241 {
 242         wait_for_pci_ready();
 243         return 1;               /* return 1 for host controller */
 244 }
 245 #endif /* defined(CONFIG_PCI) */
 246
 247 /*************************************************************************
 248  *  pci_master_init
 249  *
 250  ************************************************************************/
 251 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 252 void pci_master_init(struct pci_controller *hose)
 253 {
 254         /*--------------------------------------------------------------------------+
 255           | PowerPC440 PCI Master configuration.
 256           | Map PLB/processor addresses to PCI memory space.
 257           |   PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
 258           |   Use byte reversed out routines to handle endianess.
 259           | Make this region non-prefetchable.
 260           +--------------------------------------------------------------------------*/
 261         out32r( PCIX0_POM0SA, 0 ); /* disable */
 262         out32r( PCIX0_POM1SA, 0 ); /* disable */
 263         out32r( PCIX0_POM2SA, 0 ); /* disable */
 264
 265         out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */
 266         out32r(PCIX0_POM0LAH, 0x00000003);      /* PMM0 Local Address */
 267         out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 268         out32r(PCIX0_POM0PCIAH, 0x00000000);    /* PMM0 PCI High Address */
 269         out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1);    /* 256MB + enable region */
 270
 271         out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2);        /* PMM0 Local Address */
 272         out32r(PCIX0_POM1LAH, 0x00000003);      /* PMM0 Local Address */
 273         out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 274         out32r(PCIX0_POM1PCIAH, 0x00000000);    /* PMM0 PCI High Address */
 275         out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1);    /* 256MB + enable region */
 276 }
 277 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 278
 279 #ifdef CONFIG_POST
 280 /*
 281  * Returns 1 if keys pressed to start the power-on long-running tests
 282  * Called from board_init_f().
 283  */
 284 int post_hotkeys_pressed(void)
 285 {
 286
 287         return (ctrlc());
 288 }
 289 #endif