3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <ppc_asm.tmpl>
28 #define TLB_VALID 0x00000200
30 /* Supported page sizes */
31 #define SZ_1K 0x00000000
32 #define SZ_4K 0x00000010
33 #define SZ_16K 0x00000020
34 #define SZ_64K 0x00000030
35 #define SZ_256K 0x00000040
36 #define SZ_1M 0x00000050
37 #define SZ_16M 0x00000070
38 #define SZ_256M 0x00000090
40 /* Storage attributes */
41 #define SA_W 0x00000800 /* Write-through */
42 #define SA_I 0x00000400 /* Caching inhibited */
43 #define SA_M 0x00000200 /* Memory coherence */
44 #define SA_G 0x00000100 /* Guarded */
45 #define SA_E 0x00000080 /* Endian */
48 #define AC_X 0x00000024 /* Execute */
49 #define AC_W 0x00000012 /* Write */
50 #define AC_R 0x00000009 /* Read */
52 /* Some handy macros */
54 #define EPN(e) ((e) & 0xfffffc00)
55 #define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
56 #define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
57 #define TLB2(a) ( (a)&0x00000fbf )
69 #define tlbentry(epn,sz,rpn,erpn,attr)\
70 .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
73 /**************************************************************************
76 * This table is used by the cpu boot code to setup the initial tlb
77 * entries. Rather than make broad assumptions in the cpu source tree,
78 * this table lets each board set things up however they like.
80 * Pointer to the table is returned in r1
82 *************************************************************************/
89 tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
90 tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
91 tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
92 tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
93 #ifdef CONFIG_4xx_DCACHE
94 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G)
96 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
99 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
100 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
101 tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
103 tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
106 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I )
107 tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I )
108 tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I )
111 tlbentry( CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )