board/renesas/salvator-x/salvator-x.c

   1 /*
   2  * board/renesas/salvator-x/salvator-x.c
   3  *     This file is Salvator-X/Salvator-XS board support.
   4  *
   5  * Copyright (C) 2015-2017 Renesas Electronics Corporation
   6  * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
   7  *
   8  * SPDX-License-Identifier: GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <malloc.h>
  13 #include <netdev.h>
  14 #include <dm.h>
  15 #include <dm/platform_data/serial_sh.h>
  16 #include <asm/processor.h>
  17 #include <asm/mach-types.h>
  18 #include <asm/io.h>
  19 #include <linux/errno.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/rmobile.h>
  24 #include <asm/arch/rcar-mstp.h>
  25 #include <asm/arch/sh_sdhi.h>
  26 #include <i2c.h>
  27 #include <mmc.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define CPGWPCR 0xE6150904
  32 #define CPGWPR  0xE615090C
  33
  34 #define CLK2MHZ(clk)    (clk / 1000 / 1000)
  35 void s_init(void)
  36 {
  37         struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  38         struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  39
  40         /* Watchdog init */
  41         writel(0xA5A5A500, &rwdt->rwtcsra);
  42         writel(0xA5A5A500, &swdt->swtcsra);
  43
  44         writel(0xA5A50000, CPGWPCR);
  45         writel(0xFFFFFFFF, CPGWPR);
  46 }
  47
  48 #define GSX_MSTP112             BIT(12) /* 3DG */
  49 #define TMU0_MSTP125            BIT(25) /* secure */
  50 #define TMU1_MSTP124            BIT(24) /* non-secure */
  51 #define SCIF2_MSTP310           BIT(10) /* SCIF2 */
  52 #define ETHERAVB_MSTP812        BIT(12)
  53 #define DVFS_MSTP926            BIT(26)
  54 #define SD0_MSTP314             BIT(14)
  55 #define SD1_MSTP313             BIT(13)
  56 #define SD2_MSTP312             BIT(12) /* either MMC0 */
  57 #define SD3_MSTP311             BIT(11) /* either MMC1 */
  58 #define HSUSB_MSTP704           BIT(4)  /* HSUSB */
  59
  60 #define SD0CKCR                 0xE6150074
  61 #define SD1CKCR                 0xE6150078
  62 #define SD2CKCR                 0xE6150268
  63 #define SD3CKCR                 0xE615026C
  64
  65 int board_early_init_f(void)
  66 {
  67         /* TMU0,1 */            /* which use ? */
  68         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
  69         /* SCIF2 */
  70         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
  71         /* EHTERAVB */
  72         mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
  73         /* eMMC */
  74         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
  75         /* SDHI0, 3 */
  76         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
  77
  78         writel(1, SD0CKCR);
  79         writel(1, SD1CKCR);
  80         writel(1, SD2CKCR);
  81         writel(1, SD3CKCR);
  82
  83 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
  84         /* DVFS for reset */
  85         mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
  86 #endif
  87         return 0;
  88 }
  89
  90 /* SYSC */
  91 /* R/- 32 Power status register 2(3DG) */
  92 #define SYSC_PWRSR2     0xE6180100
  93 /* -/W 32 Power resume control register 2 (3DG) */
  94 #define SYSC_PWRONCR2   0xE618010C
  95
  96 /* HSUSB block registers */
  97 #define HSUSB_REG_LPSTS                 0xE6590102
  98 #define HSUSB_REG_LPSTS_SUSPM_NORMAL    BIT(14)
  99 #define HSUSB_REG_UGCTRL2               0xE6590184
 100 #define HSUSB_REG_UGCTRL2_USB0SEL       0x30
 101 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI  0x10
 102
 103 int board_init(void)
 104 {
 105         /* adress of boot parameters */
 106         gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
 107
 108         /* Init PFC controller */
 109 #if defined(CONFIG_R8A7795)
 110         r8a7795_pinmux_init();
 111 #elif defined(CONFIG_R8A7796)
 112         r8a7796_pinmux_init();
 113 #endif
 114
 115 #if defined(CONFIG_R8A7795)
 116         /* GSX: force power and clock supply */
 117         writel(0x0000001F, SYSC_PWRONCR2);
 118         while (readl(SYSC_PWRSR2) != 0x000003E0)
 119                 mdelay(20);
 120
 121         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
 122 #endif
 123
 124         /* USB1 pull-up */
 125         setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
 126
 127         /* Configure the HSUSB block */
 128         mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
 129         /* Choice USB0SEL */
 130         clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
 131                         HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
 132         /* low power status */
 133         setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
 134
 135 #ifdef CONFIG_RENESAS_RAVB
 136         /* EtherAVB Enable */
 137         /* GPSR2 */
 138         gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
 139         gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
 140         gpio_request(GPIO_GFN_AVB_LINK, NULL);
 141         gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
 142         gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
 143         gpio_request(GPIO_GFN_AVB_MDC, NULL);
 144
 145         /* IPSR0 */
 146         gpio_request(GPIO_IFN_AVB_MDC, NULL);
 147         gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
 148         gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
 149         gpio_request(GPIO_IFN_AVB_LINK, NULL);
 150         gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
 151         gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
 152         /* IPSR1 */
 153         gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
 154         /* IPSR2 */
 155         gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
 156         /* IPSR3 */
 157         gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
 158
 159 #if defined(CONFIG_R8A7795)
 160         /* USB2_OVC */
 161         gpio_request(GPIO_GP_6_15, NULL);
 162         gpio_direction_input(GPIO_GP_6_15);
 163
 164         /* USB2_PWEN */
 165         gpio_request(GPIO_GP_6_14, NULL);
 166         gpio_direction_output(GPIO_GP_6_14, 1);
 167         gpio_set_value(GPIO_GP_6_14, 1);
 168 #endif
 169         /* AVB_PHY_RST */
 170         gpio_request(GPIO_GP_2_10, NULL);
 171         gpio_direction_output(GPIO_GP_2_10, 0);
 172         mdelay(20);
 173         gpio_set_value(GPIO_GP_2_10, 1);
 174         udelay(1);
 175 #endif
 176
 177 #ifdef CONFIG_MMC
 178         /* SDHI0 */
 179         gpio_request(GPIO_GFN_SD0_DAT0, NULL);
 180         gpio_request(GPIO_GFN_SD0_DAT1, NULL);
 181         gpio_request(GPIO_GFN_SD0_DAT2, NULL);
 182         gpio_request(GPIO_GFN_SD0_DAT3, NULL);
 183         gpio_request(GPIO_GFN_SD0_CLK, NULL);
 184         gpio_request(GPIO_GFN_SD0_CMD, NULL);
 185         gpio_request(GPIO_GFN_SD0_CD, NULL);
 186         gpio_request(GPIO_GFN_SD0_WP, NULL);
 187
 188         gpio_request(GPIO_GP_5_2, NULL);
 189         gpio_request(GPIO_GP_5_1, NULL);
 190         gpio_direction_output(GPIO_GP_5_2, 1);  /* power on */
 191         gpio_direction_output(GPIO_GP_5_1, 1);  /* 1: 3.3V, 0: 1.8V */
 192
 193         /* SDHI1/SDHI2 eMMC */
 194         gpio_request(GPIO_GFN_SD1_DAT0, NULL);
 195         gpio_request(GPIO_GFN_SD1_DAT1, NULL);
 196         gpio_request(GPIO_GFN_SD1_DAT2, NULL);
 197         gpio_request(GPIO_GFN_SD1_DAT3, NULL);
 198         gpio_request(GPIO_GFN_SD2_DAT0, NULL);
 199         gpio_request(GPIO_GFN_SD2_DAT1, NULL);
 200         gpio_request(GPIO_GFN_SD2_DAT2, NULL);
 201         gpio_request(GPIO_GFN_SD2_DAT3, NULL);
 202         gpio_request(GPIO_GFN_SD2_CLK, NULL);
 203 #if defined(CONFIG_R8A7795)
 204         gpio_request(GPIO_GFN_SD2_CMD, NULL);
 205 #elif defined(CONFIG_R8A7796)
 206         gpio_request(GPIO_FN_SD2_CMD, NULL);
 207 #else
 208 #error Only R8A7795 and R87796 is supported
 209 #endif
 210         gpio_request(GPIO_GP_5_3, NULL);
 211         gpio_request(GPIO_GP_5_9, NULL);
 212         gpio_direction_output(GPIO_GP_5_3, 0);  /* 1: 3.3V, 0: 1.8V */
 213         gpio_direction_output(GPIO_GP_5_9, 0);  /* 1: 3.3V, 0: 1.8V */
 214
 215 #if defined(CONFIG_R8A7795)
 216         /* SDHI3 */
 217         gpio_request(GPIO_GFN_SD3_DAT0, NULL);  /* GP_4_9 */
 218         gpio_request(GPIO_GFN_SD3_DAT1, NULL);  /* GP_4_10 */
 219         gpio_request(GPIO_GFN_SD3_DAT2, NULL);  /* GP_4_11 */
 220         gpio_request(GPIO_GFN_SD3_DAT3, NULL);  /* GP_4_12 */
 221         gpio_request(GPIO_GFN_SD3_CLK, NULL);   /* GP_4_7 */
 222         gpio_request(GPIO_GFN_SD3_CMD, NULL);   /* GP_4_8 */
 223 #elif defined(CONFIG_R8A7796)
 224         gpio_request(GPIO_FN_SD3_DAT0, NULL);   /* GP_4_9 */
 225         gpio_request(GPIO_FN_SD3_DAT1, NULL);   /* GP_4_10 */
 226         gpio_request(GPIO_FN_SD3_DAT2, NULL);   /* GP_4_11 */
 227         gpio_request(GPIO_FN_SD3_DAT3, NULL);   /* GP_4_12 */
 228         gpio_request(GPIO_FN_SD3_CLK, NULL);    /* GP_4_7 */
 229         gpio_request(GPIO_FN_SD3_CMD, NULL);    /* GP_4_8 */
 230 #else
 231 #error Only R8A7795 and R87796 is supported
 232 #endif
 233         /* IPSR10 */
 234         gpio_request(GPIO_FN_SD3_CD, NULL);
 235         gpio_request(GPIO_FN_SD3_WP, NULL);
 236
 237         gpio_request(GPIO_GP_3_15, NULL);
 238         gpio_request(GPIO_GP_3_14, NULL);
 239         gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
 240         gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
 241 #endif
 242
 243         return 0;
 244 }
 245
 246 int dram_init(void)
 247 {
 248         gd->ram_size = PHYS_SDRAM_1_SIZE;
 249 #if (CONFIG_NR_DRAM_BANKS >= 2)
 250         gd->ram_size += PHYS_SDRAM_2_SIZE;
 251 #endif
 252 #if (CONFIG_NR_DRAM_BANKS >= 3)
 253         gd->ram_size += PHYS_SDRAM_3_SIZE;
 254 #endif
 255 #if (CONFIG_NR_DRAM_BANKS >= 4)
 256         gd->ram_size += PHYS_SDRAM_4_SIZE;
 257 #endif
 258
 259         return 0;
 260 }
 261
 262 int dram_init_banksize(void)
 263 {
 264         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 265         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 266 #if (CONFIG_NR_DRAM_BANKS >= 2)
 267         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 268         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 269 #endif
 270 #if (CONFIG_NR_DRAM_BANKS >= 3)
 271         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 272         gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
 273 #endif
 274 #if (CONFIG_NR_DRAM_BANKS >= 4)
 275         gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 276         gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
 277 #endif
 278         return 0;
 279 }
 280
 281 const struct rmobile_sysinfo sysinfo = {
 282         CONFIG_RCAR_BOARD_STRING
 283 };
 284
 285 #define RST_BASE        0xE6160000
 286 #define RST_CA57RESCNT  (RST_BASE + 0x40)
 287 #define RST_CA53RESCNT  (RST_BASE + 0x44)
 288 #define RST_RSTOUTCR    (RST_BASE + 0x58)
 289 #define RST_CODE        0xA5A5000F
 290
 291 void reset_cpu(ulong addr)
 292 {
 293 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
 294         i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
 295 #else
 296         /* only CA57 ? */
 297         writel(RST_CODE, RST_CA57RESCNT);
 298 #endif
 299 }