board/renesas/silk/silk.c

   1 /*
   2  * board/renesas/silk/silk.c
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corporation
   5  * Copyright (C) 2015 Cogent Embedded, Inc.
   6  *
   7  * SPDX-License-Identifier: GPL-2.0
   8  */
   9
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <asm/processor.h>
  13 #include <asm/mach-types.h>
  14 #include <asm/io.h>
  15 #include <asm/errno.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/gpio.h>
  18 #include <asm/arch/rmobile.h>
  19 #include <asm/arch/rcar-mstp.h>
  20 #include <asm/arch/mmc.h>
  21 #include <netdev.h>
  22 #include <miiphy.h>
  23 #include <i2c.h>
  24 #include <div64.h>
  25 #include "qos.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define CLK2MHZ(clk)    (clk / 1000 / 1000)
  30 void s_init(void)
  31 {
  32         struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  33         struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  34
  35         /* Watchdog init */
  36         writel(0xA5A5A500, &rwdt->rwtcsra);
  37         writel(0xA5A5A500, &swdt->swtcsra);
  38
  39         /* QoS */
  40         qos_init();
  41
  42 #ifndef CONFIG_DCACHE_OFF
  43         /*
  44          * The caches are disabled when ACTLR.SMP is set to 0
  45          * regardless of the value of the SCTLR.C (cache enable bit)
  46          * on Cortex-A7 MPCore
  47          */
  48         asm volatile(
  49                 "mrc    15, 0, r0, c1, c0, 1\n"         /* read ACTLR */
  50                 "orr    r0, r0, #(1 << 6)\n"            /* set ACTLR.SMP bit */
  51                 "mcr    p15, 0, r0, c1, c0, 1\n");      /* write ACTLR */
  52 #endif
  53 }
  54
  55 #define TMU0_MSTP125    (1 << 25)
  56 #define SCIF2_MSTP719   (1 << 19)
  57 #define ETHER_MSTP813   (1 << 13)
  58 #define IIC1_MSTP323    (1 << 23)
  59 #define MMC0_MSTP315    (1 << 15)
  60
  61 int board_early_init_f(void)
  62 {
  63         /* TMU */
  64         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  65
  66         /* SCIF2 */
  67         mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
  68
  69         /* ETHER */
  70         mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
  71
  72         /* IIC1 / sh-i2c ch1 */
  73         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
  74
  75 #ifdef CONFIG_SH_MMCIF
  76         /* MMC */
  77         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
  78 #endif
  79         return 0;
  80 }
  81
  82 int board_init(void)
  83 {
  84         /* adress of boot parameters */
  85         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  86
  87         /* Init PFC controller */
  88         r8a7794_pinmux_init();
  89
  90         /* Ether Enable */
  91         gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
  92         gpio_request(GPIO_FN_ETH_RX_ER, NULL);
  93         gpio_request(GPIO_FN_ETH_RXD0, NULL);
  94         gpio_request(GPIO_FN_ETH_RXD1, NULL);
  95         gpio_request(GPIO_FN_ETH_LINK, NULL);
  96         gpio_request(GPIO_FN_ETH_REFCLK, NULL);
  97         gpio_request(GPIO_FN_ETH_MDIO, NULL);
  98         gpio_request(GPIO_FN_ETH_TXD1, NULL);
  99         gpio_request(GPIO_FN_ETH_TX_EN, NULL);
 100         gpio_request(GPIO_FN_ETH_MAGIC, NULL);
 101         gpio_request(GPIO_FN_ETH_TXD0, NULL);
 102         gpio_request(GPIO_FN_ETH_MDC, NULL);
 103         gpio_request(GPIO_FN_IRQ8, NULL);
 104
 105         /* PHY reset */
 106         gpio_request(GPIO_GP_1_24, NULL);
 107         gpio_direction_output(GPIO_GP_1_24, 0);
 108         mdelay(20);
 109         gpio_set_value(GPIO_GP_1_24, 1);
 110         udelay(1);
 111
 112         return 0;
 113 }
 114
 115 #define CXR24 0xEE7003C0 /* MAC address high register */
 116 #define CXR25 0xEE7003C8 /* MAC address low register */
 117 int board_eth_init(bd_t *bis)
 118 {
 119 #ifdef CONFIG_SH_ETHER
 120         int ret = -ENODEV;
 121         u32 val;
 122         unsigned char enetaddr[6];
 123
 124         ret = sh_eth_initialize(bis);
 125         if (!eth_getenv_enetaddr("ethaddr", enetaddr))
 126                 return ret;
 127
 128         /* Set Mac address */
 129         val = enetaddr[0] << 24 | enetaddr[1] << 16 |
 130                 enetaddr[2] << 8 | enetaddr[3];
 131         writel(val, CXR24);
 132
 133         val = enetaddr[4] << 8 | enetaddr[5];
 134         writel(val, CXR25);
 135
 136         return ret;
 137 #else
 138         return 0;
 139 #endif
 140 }
 141
 142 int board_mmc_init(bd_t *bis)
 143 {
 144         int ret = 0;
 145
 146 #ifdef CONFIG_SH_MMCIF
 147         /* MMC0 */
 148         gpio_request(GPIO_GP_4_31, NULL);
 149         gpio_set_value(GPIO_GP_4_31, 1);
 150
 151         ret = mmcif_mmc_init();
 152 #endif
 153         return ret;
 154 }
 155
 156 int dram_init(void)
 157 {
 158         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 159
 160         return 0;
 161 }
 162
 163 const struct rmobile_sysinfo sysinfo = {
 164         CONFIG_RMOBILE_BOARD_STRING
 165 };
 166
 167 void reset_cpu(ulong addr)
 168 {
 169         u8 val;
 170
 171         i2c_set_bus_num(1); /* PowerIC connected to ch1 */
 172         i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 173         val |= 0x02;
 174         i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 175 }