2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/fsl_ddr_sdram.h>
12 #include <asm/fsl_ddr_dimm_params.h>
14 void fsl_ddr_board_options(memctl_options_t
*popts
,
16 unsigned int ctrl_num
)
19 * Factors to consider for clock adjust:
20 * - number of chips on bus
25 * This needs to be determined on a board-by-board basis.
29 popts
->clk_adjust
= 7;
32 * Factors to consider for CPO:
36 popts
->cpo_override
= 10;
39 * Factors to consider for write data delay:
49 popts
->write_data_delay
= 3;
52 * Factors to consider for half-strength driver enable:
53 * - number of DIMMs installed
55 popts
->half_strength_driver_enable
= 0;
58 #if !defined(CONFIG_SPD_EEPROM)
60 * fixed_sdram init -- doesn't use serial presence detect.
61 * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
63 phys_size_t
fixed_sdram(void)
65 volatile ccsr_ddr_t
*ddr
= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR
);
67 out_be32(&ddr
->cs0_bnds
, 0x0000007f);
68 out_be32(&ddr
->cs1_bnds
, 0x008000ff);
69 out_be32(&ddr
->cs2_bnds
, 0x00000000);
70 out_be32(&ddr
->cs3_bnds
, 0x00000000);
72 out_be32(&ddr
->cs0_config
, 0x80010101);
73 out_be32(&ddr
->cs1_config
, 0x80010101);
74 out_be32(&ddr
->cs2_config
, 0x00000000);
75 out_be32(&ddr
->cs3_config
, 0x00000000);
77 out_be32(&ddr
->timing_cfg_3
, 0x00000000);
78 out_be32(&ddr
->timing_cfg_0
, 0x00220802);
79 out_be32(&ddr
->timing_cfg_1
, 0x38377322);
80 out_be32(&ddr
->timing_cfg_2
, 0x0fa044C7);
82 out_be32(&ddr
->sdram_cfg
, 0x4300C000);
83 out_be32(&ddr
->sdram_cfg_2
, 0x24401000);
85 out_be32(&ddr
->sdram_mode
, 0x23C00542);
86 out_be32(&ddr
->sdram_mode_2
, 0x00000000);
88 out_be32(&ddr
->sdram_interval
, 0x05080100);
89 out_be32(&ddr
->sdram_md_cntl
, 0x00000000);
90 out_be32(&ddr
->sdram_data_init
, 0x00000000);
91 out_be32(&ddr
->sdram_clk_cntl
, 0x03800000);
92 asm("sync;isync;msync");
96 /* Enable ECC checking */
97 out_be32(&ddr
->sdram_cfg
, CONFIG_SYS_DDR_CONTROL
| 0x20000000);
99 out_be32(&ddr
->sdram_cfg
, CONFIG_SYS_DDR_CONTROL
);
102 return CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024;