2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
5 * Copyright 2004, 2007 Freescale Semiconductor.
7 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
32 #include <asm/immap_fsl_pci.h>
33 #include <asm/fsl_ddr_sdram.h>
34 #include <spd_sdram.h>
37 #include <fdt_support.h>
39 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
40 extern void ddr_enable_ecc(unsigned int dram_size
);
43 DECLARE_GLOBAL_DATA_PTR
;
45 void local_bus_init(void);
46 void sdram_init(void);
47 long int fixed_sdram (void);
49 int board_early_init_f (void)
56 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
57 volatile ccsr_local_ecm_t
*ecm
= (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR
);
58 volatile u_char
*rev
= (void *)CONFIG_SYS_BD_REV
;
60 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
64 * Initialize local bus.
69 * Fix CPU2 errata: A core hang possible while executing a
70 * msync instruction and a snoopable transaction from an I/O
71 * master tagged to make quick forward progress is present.
73 ecm
->eebpcr
|= (1 << 16);
76 * Hack TSEC 3 and 4 IO voltages.
78 gur
->tsec34ioovcr
= 0xe7e0; /* 1110 0111 1110 0xxx */
80 ecm
->eedr
= 0xffffffff; /* clear ecm errors */
81 ecm
->eeer
= 0xffffffff; /* enable ecm errors */
86 initdram(int board_type
)
90 puts("Initializing\n");
92 #if defined(CONFIG_DDR_DLL)
95 * Work around to stabilize DDR DLL MSYNC_IN.
96 * Errata DDR9 seems to have been fixed.
97 * This is now the workaround for Errata DDR11:
98 * Override DLL = 1, Course Adj = 1, Tap Select = 0
101 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
103 gur
->ddrdllcr
= 0x81000000;
104 asm("sync;isync;msync");
109 #if defined(CONFIG_SPD_EEPROM)
110 dram_size
= fsl_ddr_sdram();
111 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
112 dram_size
*= 0x100000;
114 dram_size
= fixed_sdram ();
117 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
119 * Initialize and enable DDR ECC.
121 ddr_enable_ecc(dram_size
);
124 * SDRAM Initialization
133 * Initialize Local Bus
138 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
139 volatile ccsr_lbc_t
*lbc
= (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR
);
145 get_sys_info(&sysinfo
);
146 clkdiv
= (lbc
->lcrr
& 0x0f) * 2;
147 lbc_hz
= sysinfo
.freqSystemBus
/ 1000000 / clkdiv
;
149 gur
->lbiuiplldcr1
= 0x00078080;
151 gur
->lbiuiplldcr0
= 0x7c0f1bf0;
152 } else if (clkdiv
== 8) {
153 gur
->lbiuiplldcr0
= 0x6c0f1bf0;
154 } else if (clkdiv
== 4) {
155 gur
->lbiuiplldcr0
= 0x5c0f1bf0;
158 lbc
->lcrr
|= 0x00030000;
160 asm("sync;isync;msync");
162 lbc
->ltesr
= 0xffffffff; /* Clear LBC error interrupts */
163 lbc
->lteir
= 0xffffffff; /* Enable LBC error interrupts */
167 * Initialize SDRAM memory on the Local Bus.
172 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
175 volatile ccsr_lbc_t
*lbc
= (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR
);
176 uint
*sdram_addr
= (uint
*)CONFIG_SYS_LBC_SDRAM_BASE
;
181 print_size (CONFIG_SYS_LBC_SDRAM_SIZE
* 1024 * 1024, "\n");
184 * Setup SDRAM Base and Option Registers
186 lbc
->or3
= CONFIG_SYS_OR3_PRELIM
;
189 lbc
->br3
= CONFIG_SYS_BR3_PRELIM
;
192 lbc
->lbcr
= CONFIG_SYS_LBC_LBCR
;
196 lbc
->lsrt
= CONFIG_SYS_LBC_LSRT
;
197 lbc
->mrtpr
= CONFIG_SYS_LBC_MRTPR
;
201 * MPC8548 uses "new" 15-16 style addressing.
203 lsdmr_common
= CONFIG_SYS_LBC_LSDMR_COMMON
;
204 lsdmr_common
|= CONFIG_SYS_LBC_LSDMR_BSMA1516
;
207 * Issue PRECHARGE ALL command.
209 lbc
->lsdmr
= lsdmr_common
| CONFIG_SYS_LBC_LSDMR_OP_PCHALL
;
212 ppcDcbf((unsigned long) sdram_addr
);
216 * Issue 8 AUTO REFRESH commands.
218 for (idx
= 0; idx
< 8; idx
++) {
219 lbc
->lsdmr
= lsdmr_common
| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH
;
222 ppcDcbf((unsigned long) sdram_addr
);
227 * Issue 8 MODE-set command.
229 lbc
->lsdmr
= lsdmr_common
| CONFIG_SYS_LBC_LSDMR_OP_MRW
;
232 ppcDcbf((unsigned long) sdram_addr
);
236 * Issue NORMAL OP command.
238 lbc
->lsdmr
= lsdmr_common
| CONFIG_SYS_LBC_LSDMR_OP_NORMAL
;
241 ppcDcbf((unsigned long) sdram_addr
);
242 udelay(200); /* Overkill. Must wait > 200 bus cycles */
244 #endif /* enable SDRAM init */
247 #if defined(CONFIG_SYS_DRAM_TEST)
251 uint
*pstart
= (uint
*) CONFIG_SYS_MEMTEST_START
;
252 uint
*pend
= (uint
*) CONFIG_SYS_MEMTEST_END
;
255 printf("Testing DRAM from 0x%08x to 0x%08x\n",
256 CONFIG_SYS_MEMTEST_START
,
257 CONFIG_SYS_MEMTEST_END
);
259 printf("DRAM test phase 1:\n");
260 for (p
= pstart
; p
< pend
; p
++)
263 for (p
= pstart
; p
< pend
; p
++) {
264 if (*p
!= 0xaaaaaaaa) {
265 printf ("DRAM test fails at: %08x\n", (uint
) p
);
270 printf("DRAM test phase 2:\n");
271 for (p
= pstart
; p
< pend
; p
++)
274 for (p
= pstart
; p
< pend
; p
++) {
275 if (*p
!= 0x55555555) {
276 printf ("DRAM test fails at: %08x\n", (uint
) p
);
281 printf("DRAM test passed.\n");
286 #if !defined(CONFIG_SPD_EEPROM)
287 /*************************************************************************
288 * fixed_sdram init -- doesn't use serial presence detect.
289 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
290 ************************************************************************/
291 long int fixed_sdram (void)
293 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
295 volatile ccsr_ddr_t
*ddr
= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR
);
297 ddr
->cs0_bnds
= 0x0000007f;
298 ddr
->cs1_bnds
= 0x008000ff;
299 ddr
->cs2_bnds
= 0x00000000;
300 ddr
->cs3_bnds
= 0x00000000;
301 ddr
->cs0_config
= 0x80010101;
302 ddr
->cs1_config
= 0x80010101;
303 ddr
->cs2_config
= 0x00000000;
304 ddr
->cs3_config
= 0x00000000;
305 ddr
->timing_cfg_3
= 0x00000000;
306 ddr
->timing_cfg_0
= 0x00220802;
307 ddr
->timing_cfg_1
= 0x38377322;
308 ddr
->timing_cfg_2
= 0x0fa044C7;
309 ddr
->sdram_cfg
= 0x4300C000;
310 ddr
->sdram_cfg_2
= 0x24401000;
311 ddr
->sdram_mode
= 0x23C00542;
312 ddr
->sdram_mode_2
= 0x00000000;
313 ddr
->sdram_interval
= 0x05080100;
314 ddr
->sdram_md_cntl
= 0x00000000;
315 ddr
->sdram_data_init
= 0x00000000;
316 ddr
->sdram_clk_cntl
= 0x03800000;
317 asm("sync;isync;msync");
320 #if defined (CONFIG_DDR_ECC)
321 /* Enable ECC checking */
322 ddr
->sdram_cfg
= (CONFIG_SYS_DDR_CONTROL
| 0x20000000);
324 ddr
->sdram_cfg
= CONFIG_SYS_DDR_CONTROL
;
327 return CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024;
331 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
332 /* For some reason the Tundra PCI bridge shows up on itself as a
333 * different device. Work around that by refusing to configure it.
335 void dummy_func(struct pci_controller
* hose
, pci_dev_t dev
, struct pci_config_table
*tab
) { }
337 static struct pci_config_table pci_sbc8548_config_table
[] = {
338 {0x10e3, 0x0513, PCI_ANY_ID
, 1, 3, PCI_ANY_ID
, dummy_func
, {0,0,0}},
339 {0x1106, 0x0686, PCI_ANY_ID
, 1, VIA_ID
, 0, mpc85xx_config_via
, {0,0,0}},
340 {0x1106, 0x0571, PCI_ANY_ID
, 1, VIA_ID
, 1,
341 mpc85xx_config_via_usbide
, {0,0,0}},
342 {0x1105, 0x3038, PCI_ANY_ID
, 1, VIA_ID
, 2,
343 mpc85xx_config_via_usb
, {0,0,0}},
344 {0x1106, 0x3038, PCI_ANY_ID
, 1, VIA_ID
, 3,
345 mpc85xx_config_via_usb2
, {0,0,0}},
346 {0x1106, 0x3058, PCI_ANY_ID
, 1, VIA_ID
, 5,
347 mpc85xx_config_via_power
, {0,0,0}},
348 {0x1106, 0x3068, PCI_ANY_ID
, 1, VIA_ID
, 6,
349 mpc85xx_config_via_ac97
, {0,0,0}},
353 static struct pci_controller pci1_hose
= {
354 config_table
: pci_sbc8548_config_table
};
355 #endif /* CONFIG_PCI */
358 static struct pci_controller pci2_hose
;
359 #endif /* CONFIG_PCI2 */
362 static struct pci_controller pcie1_hose
;
363 #endif /* CONFIG_PCIE1 */
365 int first_free_busno
=0;
370 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
374 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCI1_ADDR
;
375 extern void fsl_pci_init(struct pci_controller
*hose
);
376 struct pci_controller
*hose
= &pci1_hose
;
377 struct pci_config_table
*table
;
379 uint pci_32
= gur
->pordevsr
& MPC85xx_PORDEVSR_PCI1_PCI32
; /* PORDEVSR[15] */
380 uint pci_arb
= gur
->pordevsr
& MPC85xx_PORDEVSR_PCI1_ARB
; /* PORDEVSR[14] */
381 uint pci_clk_sel
= gur
->porpllsr
& MPC85xx_PORDEVSR_PCI1_SPD
; /* PORPLLSR[16] */
383 uint pci_agent
= (host_agent
== 3) || (host_agent
== 4 ) || (host_agent
== 6);
385 uint pci_speed
= get_clock_freq (); /* PCI PSPEED in [4:5] */
387 if (!(gur
->devdisr
& MPC85xx_DEVDISR_PCI1
)) {
388 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
390 (pci_speed
== 33333000) ? "33" :
391 (pci_speed
== 66666000) ? "66" : "unknown",
392 pci_clk_sel
? "sync" : "async",
393 pci_agent
? "agent" : "host",
394 pci_arb
? "arbiter" : "external-arbiter"
399 pci_set_region(hose
->regions
+ 0,
400 CONFIG_SYS_PCI_MEMORY_BUS
,
401 CONFIG_SYS_PCI_MEMORY_PHYS
,
402 CONFIG_SYS_PCI_MEMORY_SIZE
,
403 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
406 /* outbound memory */
407 pci_set_region(hose
->regions
+ 1,
408 CONFIG_SYS_PCI1_MEM_BASE
,
409 CONFIG_SYS_PCI1_MEM_PHYS
,
410 CONFIG_SYS_PCI1_MEM_SIZE
,
414 pci_set_region(hose
->regions
+ 2,
415 CONFIG_SYS_PCI1_IO_BASE
,
416 CONFIG_SYS_PCI1_IO_PHYS
,
417 CONFIG_SYS_PCI1_IO_SIZE
,
419 hose
->region_count
= 3;
421 /* relocate config table pointers */
422 hose
->config_table
= \
423 (struct pci_config_table
*)((uint
)hose
->config_table
+ gd
->reloc_off
);
424 for (table
= hose
->config_table
; table
&& table
->vendor
; table
++)
425 table
->config_device
+= gd
->reloc_off
;
427 hose
->first_busno
=first_free_busno
;
428 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
431 first_free_busno
=hose
->last_busno
+1;
432 printf ("PCI on bus %02x - %02x\n",hose
->first_busno
,hose
->last_busno
);
433 #ifdef CONFIG_PCIX_CHECK
434 if (!(gur
->pordevsr
& PORDEVSR_PCI
)) {
436 if (CONFIG_SYS_CLK_FREQ
< 66000000)
437 printf("PCI-X will only work at 66 MHz\n");
439 reg16
= PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
440 | PCI_X_CMD_ERO
| PCI_X_CMD_DPERR_E
;
441 pci_hose_write_config_word(hose
, bus
, PCIX_COMMAND
, reg16
);
445 printf (" PCI: disabled\n");
449 gur
->devdisr
|= MPC85xx_DEVDISR_PCI1
; /* disable */
454 uint pci2_clk_sel
= gur
->porpllsr
& 0x4000; /* PORPLLSR[17] */
455 uint pci_dual
= get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
457 printf (" PCI2: 32 bit, 66 MHz, %s\n",
458 pci2_clk_sel
? "sync" : "async");
460 printf (" PCI2: disabled\n");
464 gur
->devdisr
|= MPC85xx_DEVDISR_PCI2
; /* disable */
465 #endif /* CONFIG_PCI2 */
469 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCIE1_ADDR
;
470 extern void fsl_pci_init(struct pci_controller
*hose
);
471 struct pci_controller
*hose
= &pcie1_hose
;
472 int pcie_ep
= (host_agent
== 0) || (host_agent
== 2 ) || (host_agent
== 3);
474 int pcie_configured
= io_sel
>= 1;
476 if (pcie_configured
&& !(gur
->devdisr
& MPC85xx_DEVDISR_PCIE
)){
477 printf ("\n PCIE connected to slot as %s (base address %x)",
478 pcie_ep
? "End Point" : "Root Complex",
481 if (pci
->pme_msg_det
) {
482 pci
->pme_msg_det
= 0xffffffff;
483 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
488 pci_set_region(hose
->regions
+ 0,
489 CONFIG_SYS_PCI_MEMORY_BUS
,
490 CONFIG_SYS_PCI_MEMORY_PHYS
,
491 CONFIG_SYS_PCI_MEMORY_SIZE
,
492 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
494 /* outbound memory */
495 pci_set_region(hose
->regions
+ 1,
496 CONFIG_SYS_PCIE1_MEM_BASE
,
497 CONFIG_SYS_PCIE1_MEM_PHYS
,
498 CONFIG_SYS_PCIE1_MEM_SIZE
,
502 pci_set_region(hose
->regions
+ 2,
503 CONFIG_SYS_PCIE1_IO_BASE
,
504 CONFIG_SYS_PCIE1_IO_PHYS
,
505 CONFIG_SYS_PCIE1_IO_SIZE
,
508 hose
->region_count
= 3;
510 hose
->first_busno
=first_free_busno
;
511 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
514 printf ("PCIE on bus %d - %d\n",hose
->first_busno
,hose
->last_busno
);
516 first_free_busno
=hose
->last_busno
+1;
519 printf (" PCIE: disabled\n");
523 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE
; /* disable */
528 int last_stage_init(void)
533 #if defined(CONFIG_OF_BOARD_SETUP)
535 ft_pci_setup(void *blob
, bd_t
*bd
)
539 node
= fdt_path_offset(blob
, "/aliases");
544 path
= fdt_getprop(blob
, node
, "pci0", NULL
);
546 tmp
[1] = pci1_hose
.last_busno
- pci1_hose
.first_busno
;
547 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
552 path
= fdt_getprop(blob
, node
, "pci1", NULL
);
554 tmp
[1] = pcie1_hose
.last_busno
- pcie1_hose
.first_busno
;
555 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
562 #if defined(CONFIG_OF_BOARD_SETUP)
564 ft_board_setup(void *blob
, bd_t
*bd
)
566 ft_cpu_setup(blob
, bd
);
568 ft_pci_setup(blob
, bd
);