2 * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
23 #include <asm/arch/imx-regs.h>
30 /* Change PERCLK1DIV to 14 ie 14+1 */
32 ldr r1, =CONFIG_SYS_PCDR_VAL
35 /* set MCU PLL Control Register 0 */
38 ldr r1, =CONFIG_SYS_MPCTL0_VAL
41 /* set mpll restart bit */
57 /* set System PLL Control Register 0 */
60 ldr r1, =CONFIG_SYS_SPCTL0_VAL
63 /* set spll restart bit */
80 ldr r1, =CONFIG_SYS_CSCR_VAL
83 /* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
86 * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
87 * register 1, this stops it using the output of the PLL and thus runs at the
88 * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
89 * use the value set in the CM_OSC registers...regardless of what you set it
90 * too! Thus, although i thought i was running at 140MHz, i'm actually running
93 * Slapping this into my bootloader does the trick...
95 * MRC p15,0,r0,c1,c0,0 ; read core configuration register
96 * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
97 * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
101 ORR r0,r0,#0xC0000000
105 ldr r1, =CONFIG_SYS_GPR_A_VAL
109 ldr r1, =CONFIG_SYS_GIUS_A_VAL
112 /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
115 ldr r1, =CONFIG_SYS_FMCR_VAL
119 ldr r1, =CONFIG_SYS_CS0U_VAL
123 ldr r1, =CONFIG_SYS_CS0L_VAL
127 ldr r1, =CONFIG_SYS_CS1U_VAL
131 ldr r1, =CONFIG_SYS_CS1L_VAL
135 ldr r1, =CONFIG_SYS_CS2U_VAL
139 ldr r1, =CONFIG_SYS_CS2L_VAL
143 ldr r1, =CONFIG_SYS_CS3U_VAL
147 ldr r1, =CONFIG_SYS_CS3L_VAL
151 ldr r1, =CONFIG_SYS_CS4U_VAL
155 ldr r1, =CONFIG_SYS_CS4L_VAL
159 ldr r1, =CONFIG_SYS_CS5U_VAL
163 ldr r1, =CONFIG_SYS_CS5L_VAL
169 ldr r1, =PRECHARGE_CMD
173 ldr r1, =0x0 /* Issue Precharge all Command */
177 ldr r1, =AUTOREFRESH_CMD
181 ldr r1, =0x0 /* Issue AutoRefresh Command */
195 ldr r0, =0x08223000 /* CAS Latency 2 */
196 ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */
200 ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */