]>
git.ipfire.org Git - people/ms/u-boot.git/blob - board/snmc/qs860t/qs860t.c
6 * Simple Network Magic Corporation, dnevil@snmc.com
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/u-boot.h>
35 /* ------------------------------------------------------------------------- */
37 static long int dram_size (long int, long int *, long int);
39 /* ------------------------------------------------------------------------- */
41 const uint sdram_table
[] =
44 * Single Read. (Offset 0 in UPMA RAM)
46 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
47 0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35,
49 * Burst Read. (Offset 8 in UPMA RAM)
51 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
52 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,
53 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
54 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
56 * Single Write. (Offset 18 in UPMA RAM)
58 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,
59 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
61 * Burst Write. (Offset 20 in UPMA RAM)
63 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
64 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04,
65 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
66 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
68 * Refresh (Offset 30 in UPMA RAM)
70 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
71 0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04,
72 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
74 * Exception. (Offset 3c in UPMA RAM)
76 0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04
79 /* ------------------------------------------------------------------------- */
83 * Check Board Identity:
85 * Test ID string (QS860T...)
96 i
= getenv_r("serial#", buf
, sizeof(buf
));
97 s
= (i
>0) ? buf
: NULL
;
99 if (!s
|| strncmp(s
, "QS860T", 6)) {
100 puts ("### No HW ID - assuming QS860T");
116 /* ------------------------------------------------------------------------- */
118 phys_size_t
initdram (int board_type
)
120 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
121 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
124 upmconfig(UPMB
, (uint
*)sdram_table
, sizeof(sdram_table
)/sizeof(uint
));
127 * Prescaler for refresh
129 memctl
->memc_mptpr
= 0x0400;
132 * Map controller bank 2 to the SDRAM address
134 memctl
->memc_or2
= CONFIG_SYS_OR2
;
135 memctl
->memc_br2
= CONFIG_SYS_BR2
;
138 /* perform SDRAM initialization sequence */
139 memctl
->memc_mbmr
= CONFIG_SYS_16M_MBMR
;
142 memctl
->memc_mar
= 0x00000088;
143 memctl
->memc_mcr
= 0x80804105; /* run precharge pattern */
146 /* Run two refresh cycles on SDRAM */
147 memctl
->memc_mbmr
= 0x18802118;
148 memctl
->memc_mcr
= 0x80804130;
149 memctl
->memc_mbmr
= 0x18802114;
150 memctl
->memc_mcr
= 0x80804106;
156 * Check for 64M SDRAM Memory Size
158 size
= dram_size (CONFIG_SYS_64M_MBMR
, (ulong
*)SDRAM_BASE
, SDRAM_64M_MAX_SIZE
);
162 * Check for 16M SDRAM Memory Size
164 if (size
!= SDRAM_64M_MAX_SIZE
) {
166 size
= dram_size (CONFIG_SYS_16M_MBMR
, (long *)SDRAM_BASE
, SDRAM_16M_MAX_SIZE
);
171 memctl
->memc_or2
= ((-size
) & 0xFFFF0000) | SDRAM_TIMING
;
181 * Also, map other memory to correct position
185 * Map the 8M Intel Flash device to chip select 1
187 memctl
->memc_or1
= CONFIG_SYS_OR1
;
188 memctl
->memc_br1
= CONFIG_SYS_BR1
;
192 * Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg
195 memctl
->memc_or3
= CONFIG_SYS_OR3
;
196 memctl
->memc_br3
= CONFIG_SYS_BR3
;
199 * Map chip selects 4, 5, 6, & 7 for external expansion connector
201 memctl
->memc_or4
= CONFIG_SYS_OR4
;
202 memctl
->memc_br4
= CONFIG_SYS_BR4
;
204 memctl
->memc_or5
= CONFIG_SYS_OR5
;
205 memctl
->memc_br5
= CONFIG_SYS_BR5
;
207 memctl
->memc_or6
= CONFIG_SYS_OR6
;
208 memctl
->memc_br6
= CONFIG_SYS_BR6
;
210 memctl
->memc_or7
= CONFIG_SYS_OR7
;
211 memctl
->memc_br7
= CONFIG_SYS_BR7
;
218 /* ------------------------------------------------------------------------- */
221 * Check memory range for valid RAM. A simple memory test determines
222 * the actually available RAM size between addresses `base' and
223 * `base + maxsize'. Some (not all) hardware errors are detected:
224 * - short between address lines
225 * - short between data lines
228 static long int dram_size (long int mbmr_value
, long int *base
, long int maxsize
)
230 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
231 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
233 memctl
->memc_mbmr
= mbmr_value
;
235 return (get_ram_size(base
, maxsize
));