board/snmc/qs860t/qs860t.c

   1 /*
   2  * (C) Copyright 2003
   3  * MuLogic B.V.
   4  *
   5  * (C) Copyright 2002
   6  * Simple Network Magic Corporation, dnevil@snmc.com
   7  *
   8  * (C) Copyright 2000
   9  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <common.h>
  31 #include <asm/u-boot.h>
  32 #include <commproc.h>
  33 #include "mpc8xx.h"
  34
  35 /* ------------------------------------------------------------------------- */
  36
  37 static long  int dram_size (long int, long int *, long int);
  38
  39 /* ------------------------------------------------------------------------- */
  40
  41 const uint sdram_table[] =
  42 {
  43         /*
  44          * Single Read. (Offset 0 in UPMA RAM)
  45          */
  46         0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
  47         0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35,
  48         /*
  49          * Burst Read. (Offset 8 in UPMA RAM)
  50          */
  51         0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
  52         0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,
  53         0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
  54         0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
  55         /*
  56          * Single Write. (Offset 18 in UPMA RAM)
  57          */
  58         0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,
  59         0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
  60         /*
  61          * Burst Write. (Offset 20 in UPMA RAM)
  62          */
  63         0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
  64         0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04,
  65         0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
  66         0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
  67         /*
  68          * Refresh  (Offset 30 in UPMA RAM)
  69          */
  70         0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  71         0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04,
  72         0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
  73         /*
  74          * Exception. (Offset 3c in UPMA RAM)
  75          */
  76         0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04
  77 };
  78
  79 /* ------------------------------------------------------------------------- */
  80
  81
  82 /*
  83  * Check Board Identity:
  84  *
  85  * Test ID string (QS860T...)
  86  *
  87  * Always return 1
  88  */
  89
  90 int checkboard (void)
  91 {
  92         char *s, *e;
  93         char buf[64];
  94         int i;
  95
  96         i = getenv_r("serial#", buf, sizeof(buf));
  97         s = (i>0) ? buf : NULL;
  98
  99         if (!s || strncmp(s, "QS860T", 6)) {
 100                 puts ("### No HW ID - assuming QS860T");
 101         } else {
 102                 for (e=s; *e; ++e) {
 103                         if (*e == ' ')
 104                         break;
 105                 }
 106
 107                 for ( ; s<e; ++s) {
 108                         putc (*s);
 109                 }
 110         }
 111         putc ('\n');
 112
 113         return (0);
 114 }
 115
 116 /* ------------------------------------------------------------------------- */
 117
 118 long int initdram (int board_type)
 119 {
 120         volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
 121         volatile memctl8xx_t *memctl = &immap->im_memctl;
 122         long int size;
 123
 124         upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 125
 126         /*
 127         * Prescaler for refresh
 128         */
 129         memctl->memc_mptpr = 0x0400;
 130
 131         /*
 132         * Map controller bank 2 to the SDRAM address
 133         */
 134         memctl->memc_or2 = CFG_OR2;
 135         memctl->memc_br2 = CFG_BR2;
 136         udelay(200);
 137
 138         /* perform SDRAM initialization sequence */
 139         memctl->memc_mbmr = CFG_16M_MBMR;
 140         udelay(100);
 141
 142         memctl->memc_mar  = 0x00000088;
 143         memctl->memc_mcr  = 0x80804105; /* run precharge pattern */
 144         udelay(1);
 145
 146         /* Run two refresh cycles on SDRAM */
 147         memctl->memc_mbmr = 0x18802118;
 148         memctl->memc_mcr  = 0x80804130;
 149         memctl->memc_mbmr = 0x18802114;
 150         memctl->memc_mcr  = 0x80804106;
 151
 152         udelay (1000);
 153
 154 #if 0
 155         /*
 156         * Check for 64M SDRAM Memory Size
 157         */
 158         size = dram_size (CFG_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE);
 159         udelay (1000);
 160
 161         /*
 162         * Check for 16M SDRAM Memory Size
 163         */
 164         if (size != SDRAM_64M_MAX_SIZE) {
 165 #endif
 166         size = dram_size (CFG_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
 167         udelay (1000);
 168 #if 0
 169         }
 170
 171         memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
 172 #endif
 173
 174
 175         udelay(10000);
 176
 177
 178 #if 0
 179
 180         /*
 181         * Also, map other memory to correct position
 182         */
 183
 184         /*
 185         * Map the 8M Intel Flash device to chip select 1
 186         */
 187         memctl->memc_or1 = CFG_OR1;
 188         memctl->memc_br1 = CFG_BR1;
 189
 190
 191         /*
 192         * Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg
 193         * to chip select 3
 194         */
 195         memctl->memc_or3 = CFG_OR3;
 196         memctl->memc_br3 = CFG_BR3;
 197
 198         /*
 199         * Map chip selects 4, 5, 6, & 7 for external expansion connector
 200         */
 201         memctl->memc_or4 = CFG_OR4;
 202         memctl->memc_br4 = CFG_BR4;
 203
 204         memctl->memc_or5 = CFG_OR5;
 205         memctl->memc_br5 = CFG_BR5;
 206
 207         memctl->memc_or6 = CFG_OR6;
 208         memctl->memc_br6 = CFG_BR6;
 209
 210         memctl->memc_or7 = CFG_OR7;
 211         memctl->memc_br7 = CFG_BR7;
 212
 213 #endif
 214
 215         return (size);
 216 }
 217
 218 /* ------------------------------------------------------------------------- */
 219
 220 /*
 221  * Check memory range for valid RAM. A simple memory test determines
 222  * the actually available RAM size between addresses `base' and
 223  * `base + maxsize'. Some (not all) hardware errors are detected:
 224  * - short between address lines
 225  * - short between data lines
 226  */
 227
 228 static long int dram_size (long int mbmr_value, long int *base, long int maxsize)
 229 {
 230         volatile immap_t *immap  = (immap_t *)CFG_IMMR;
 231         volatile memctl8xx_t *memctl = &immap->im_memctl;
 232
 233         memctl->memc_mbmr = mbmr_value;
 234
 235         return (get_ram_size(base, maxsize));
 236 }