2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
8 * Based on SPL code from Solidrun tree, which is:
9 * Author: Tungyi Lin <tungyilin1127@gmail.com>
11 * Derived from EDM_CF_IMX6 code by TechNexion,Inc
12 * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
14 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/iomux.h>
20 #include <asm/arch/mx6-pins.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/errno.h>
24 #include <asm/imx-common/iomux-v3.h>
25 #include <asm/imx-common/video.h>
27 #include <fsl_esdhc.h>
31 #include <asm/arch/crm_regs.h>
33 #include <asm/arch/sys_proto.h>
36 #include <usb/ehci-fsl.h>
38 DECLARE_GLOBAL_DATA_PTR
;
40 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
41 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
45 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
46 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
48 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
51 #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
54 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
55 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
57 #define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
58 #define USB_H1_VBUS IMX_GPIO_NR(1, 0)
62 gd
->ram_size
= imx_ddr_size();
66 static iomux_v3_cfg_t
const uart1_pads
[] = {
67 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
68 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
71 static iomux_v3_cfg_t
const usdhc2_pads
[] = {
72 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
73 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
74 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
75 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
76 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
77 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
80 static iomux_v3_cfg_t
const hb_cbi_sense
[] = {
81 /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
82 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
83 IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
86 static iomux_v3_cfg_t
const usb_pads
[] = {
87 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
90 static void setup_iomux_uart(void)
92 SETUP_IOMUX_PADS(uart1_pads
);
95 static struct fsl_esdhc_cfg usdhc_cfg
[1] = {
99 int board_mmc_getcd(struct mmc
*mmc
)
101 return 1; /* uSDHC2 is always present */
104 int board_mmc_init(bd_t
*bis
)
106 SETUP_IOMUX_PADS(usdhc2_pads
);
107 usdhc_cfg
[0].esdhc_base
= USDHC2_BASE_ADDR
;
108 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
109 gd
->arch
.sdhc_clk
= usdhc_cfg
[0].sdhc_clk
;
111 return fsl_esdhc_initialize(bis
, &usdhc_cfg
[0]);
114 static iomux_v3_cfg_t
const enet_pads
[] = {
115 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
116 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
118 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15
| MUX_PAD_CTRL(ENET_PAD_CTRL_PD
)),
119 /* AR8035 interrupt */
120 IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
121 /* GPIO16 -> AR8035 25MHz */
122 IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
123 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
124 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
125 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
126 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
127 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
128 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
129 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
130 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL_CLK
)),
131 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
132 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_PAD_CTRL_PD
)),
133 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_PAD_CTRL_PD
)),
134 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
135 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
136 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
| MUX_PAD_CTRL(ENET_PAD_CTRL_PD
)),
137 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27
| MUX_PAD_CTRL(ENET_PAD_CTRL_PD
)),
138 IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26
| MUX_PAD_CTRL(ENET_PAD_CTRL_PD
)),
141 static void setup_iomux_enet(void)
143 SETUP_IOMUX_PADS(enet_pads
);
145 gpio_direction_output(ETH_PHY_RESET
, 0);
147 gpio_set_value(ETH_PHY_RESET
, 1);
150 int board_phy_config(struct phy_device
*phydev
)
152 if (phydev
->drv
->config
)
153 phydev
->drv
->config(phydev
);
158 /* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
159 #define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4))
161 int board_eth_init(bd_t
*bis
)
163 struct iomuxc
*const iomuxc_regs
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
165 struct phy_device
*phydev
;
167 int ret
= enable_fec_anatop_clock(ENET_25MHZ
);
171 /* set gpr1[ENET_CLK_SEL] */
172 setbits_le32(&iomuxc_regs
->gpr
[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK
);
176 bus
= fec_get_miibus(IMX_FEC_BASE
, -1);
180 phydev
= phy_find_by_mask(bus
, ETH_PHY_MASK
, PHY_INTERFACE_MODE_RGMII
);
186 debug("using phy at address %d\n", phydev
->addr
);
187 ret
= fec_probe(bis
, -1, IMX_FEC_BASE
, bus
, phydev
);
200 #ifdef CONFIG_VIDEO_IPUV3
201 static void do_enable_hdmi(struct display_info_t
const *dev
)
203 imx_enable_hdmi_phy();
206 struct display_info_t
const displays
[] = {
210 .pixfmt
= IPU_PIX_FMT_RGB24
,
211 .detect
= detect_hdmi
,
212 .enable
= do_enable_hdmi
,
215 /* 1024x768@60Hz (VESA)*/
227 .vmode
= FB_VMODE_NONINTERLACED
232 size_t display_count
= ARRAY_SIZE(displays
);
234 static int setup_display(void)
236 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
238 int timeout
= 100000;
243 /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
244 setbits_le32(&ccm
->analog_pll_video
, BM_ANADIG_PLL_VIDEO_POWERDOWN
);
246 reg
= readl(&ccm
->analog_pll_video
);
247 reg
&= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT
;
248 reg
|= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
249 reg
&= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT
;
250 reg
|= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
251 writel(reg
, &ccm
->analog_pll_video
);
253 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm
->analog_pll_video_num
);
254 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm
->analog_pll_video_denom
);
256 reg
&= ~BM_ANADIG_PLL_VIDEO_POWERDOWN
;
257 writel(reg
, &ccm
->analog_pll_video
);
260 if (readl(&ccm
->analog_pll_video
) & BM_ANADIG_PLL_VIDEO_LOCK
)
263 printf("Warning: video pll lock timeout!\n");
267 reg
= readl(&ccm
->analog_pll_video
);
268 reg
|= BM_ANADIG_PLL_VIDEO_ENABLE
;
269 reg
&= ~BM_ANADIG_PLL_VIDEO_BYPASS
;
270 writel(reg
, &ccm
->analog_pll_video
);
272 /* gate ipu1_di0_clk */
273 clrbits_le32(&ccm
->CCGR3
, MXC_CCM_CCGR3_LDB_DI0_MASK
);
275 /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
276 reg
= readl(&ccm
->chsccdr
);
277 reg
&= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
|
278 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
|
279 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK
);
280 reg
|= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET
) |
281 (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET
) |
282 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET
);
283 writel(reg
, &ccm
->chsccdr
);
285 /* enable ipu1_di0_clk */
286 setbits_le32(&ccm
->CCGR3
, MXC_CCM_CCGR3_LDB_DI0_MASK
);
290 #endif /* CONFIG_VIDEO_IPUV3 */
292 #ifdef CONFIG_USB_EHCI_MX6
293 static void setup_usb(void)
295 SETUP_IOMUX_PADS(usb_pads
);
298 int board_ehci_hcd_init(int port
)
301 gpio_direction_output(USB_H1_VBUS
, 1);
307 int board_early_init_f(void)
312 #ifdef CONFIG_VIDEO_IPUV3
313 ret
= setup_display();
316 #ifdef CONFIG_USB_EHCI_MX6
324 /* address of boot parameters */
325 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
330 static bool is_hummingboard(void)
334 SETUP_IOMUX_PADS(hb_cbi_sense
);
336 gpio_direction_input(IMX_GPIO_NR(4, 9));
337 gpio_direction_input(IMX_GPIO_NR(3, 4));
339 val1
= gpio_get_value(IMX_GPIO_NR(4, 9));
340 val2
= gpio_get_value(IMX_GPIO_NR(3, 4));
343 * Machine selection -
345 * -------------------------
361 if (is_hummingboard())
362 puts("Board: MX6 Hummingboard\n");
364 puts("Board: MX6 Cubox-i\n");
369 static bool is_mx6q(void)
371 if (is_cpu_type(MXC_CPU_MX6Q
) || is_cpu_type(MXC_CPU_MX6D
))
377 int board_late_init(void)
379 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
380 if (is_hummingboard())
381 setenv("board_name", "HUMMINGBOARD");
383 setenv("board_name", "CUBOXI");
386 setenv("board_rev", "MX6Q");
388 setenv("board_rev", "MX6DL");
394 #ifdef CONFIG_SPL_BUILD
395 #include <asm/arch/mx6-ddr.h>
396 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs
= {
397 .dram_sdclk_0
= 0x00020030,
398 .dram_sdclk_1
= 0x00020030,
399 .dram_cas
= 0x00020030,
400 .dram_ras
= 0x00020030,
401 .dram_reset
= 0x00020030,
402 .dram_sdcke0
= 0x00003000,
403 .dram_sdcke1
= 0x00003000,
404 .dram_sdba2
= 0x00000000,
405 .dram_sdodt0
= 0x00003030,
406 .dram_sdodt1
= 0x00003030,
407 .dram_sdqs0
= 0x00000030,
408 .dram_sdqs1
= 0x00000030,
409 .dram_sdqs2
= 0x00000030,
410 .dram_sdqs3
= 0x00000030,
411 .dram_sdqs4
= 0x00000030,
412 .dram_sdqs5
= 0x00000030,
413 .dram_sdqs6
= 0x00000030,
414 .dram_sdqs7
= 0x00000030,
415 .dram_dqm0
= 0x00020030,
416 .dram_dqm1
= 0x00020030,
417 .dram_dqm2
= 0x00020030,
418 .dram_dqm3
= 0x00020030,
419 .dram_dqm4
= 0x00020030,
420 .dram_dqm5
= 0x00020030,
421 .dram_dqm6
= 0x00020030,
422 .dram_dqm7
= 0x00020030,
425 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs
= {
426 .dram_sdclk_0
= 0x00000028,
427 .dram_sdclk_1
= 0x00000028,
428 .dram_cas
= 0x00000028,
429 .dram_ras
= 0x00000028,
430 .dram_reset
= 0x000c0028,
431 .dram_sdcke0
= 0x00003000,
432 .dram_sdcke1
= 0x00003000,
433 .dram_sdba2
= 0x00000000,
434 .dram_sdodt0
= 0x00003030,
435 .dram_sdodt1
= 0x00003030,
436 .dram_sdqs0
= 0x00000028,
437 .dram_sdqs1
= 0x00000028,
438 .dram_sdqs2
= 0x00000028,
439 .dram_sdqs3
= 0x00000028,
440 .dram_sdqs4
= 0x00000028,
441 .dram_sdqs5
= 0x00000028,
442 .dram_sdqs6
= 0x00000028,
443 .dram_sdqs7
= 0x00000028,
444 .dram_dqm0
= 0x00000028,
445 .dram_dqm1
= 0x00000028,
446 .dram_dqm2
= 0x00000028,
447 .dram_dqm3
= 0x00000028,
448 .dram_dqm4
= 0x00000028,
449 .dram_dqm5
= 0x00000028,
450 .dram_dqm6
= 0x00000028,
451 .dram_dqm7
= 0x00000028,
454 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs
= {
455 .grp_ddr_type
= 0x000C0000,
456 .grp_ddrmode_ctl
= 0x00020000,
457 .grp_ddrpke
= 0x00000000,
458 .grp_addds
= 0x00000030,
459 .grp_ctlds
= 0x00000030,
460 .grp_ddrmode
= 0x00020000,
461 .grp_b0ds
= 0x00000030,
462 .grp_b1ds
= 0x00000030,
463 .grp_b2ds
= 0x00000030,
464 .grp_b3ds
= 0x00000030,
465 .grp_b4ds
= 0x00000030,
466 .grp_b5ds
= 0x00000030,
467 .grp_b6ds
= 0x00000030,
468 .grp_b7ds
= 0x00000030,
471 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
472 .grp_ddr_type
= 0x000c0000,
473 .grp_ddrmode_ctl
= 0x00020000,
474 .grp_ddrpke
= 0x00000000,
475 .grp_addds
= 0x00000028,
476 .grp_ctlds
= 0x00000028,
477 .grp_ddrmode
= 0x00020000,
478 .grp_b0ds
= 0x00000028,
479 .grp_b1ds
= 0x00000028,
480 .grp_b2ds
= 0x00000028,
481 .grp_b3ds
= 0x00000028,
482 .grp_b4ds
= 0x00000028,
483 .grp_b5ds
= 0x00000028,
484 .grp_b6ds
= 0x00000028,
485 .grp_b7ds
= 0x00000028,
488 /* microSOM with Dual processor and 1GB memory */
489 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib
= {
490 .p0_mpwldectrl0
= 0x00000000,
491 .p0_mpwldectrl1
= 0x00000000,
492 .p1_mpwldectrl0
= 0x00000000,
493 .p1_mpwldectrl1
= 0x00000000,
494 .p0_mpdgctrl0
= 0x0314031c,
495 .p0_mpdgctrl1
= 0x023e0304,
496 .p1_mpdgctrl0
= 0x03240330,
497 .p1_mpdgctrl1
= 0x03180260,
498 .p0_mprddlctl
= 0x3630323c,
499 .p1_mprddlctl
= 0x3436283a,
500 .p0_mpwrdlctl
= 0x36344038,
501 .p1_mpwrdlctl
= 0x422a423c,
504 /* microSOM with Quad processor and 2GB memory */
505 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib
= {
506 .p0_mpwldectrl0
= 0x00000000,
507 .p0_mpwldectrl1
= 0x00000000,
508 .p1_mpwldectrl0
= 0x00000000,
509 .p1_mpwldectrl1
= 0x00000000,
510 .p0_mpdgctrl0
= 0x0314031c,
511 .p0_mpdgctrl1
= 0x023e0304,
512 .p1_mpdgctrl0
= 0x03240330,
513 .p1_mpdgctrl1
= 0x03180260,
514 .p0_mprddlctl
= 0x3630323c,
515 .p1_mprddlctl
= 0x3436283a,
516 .p0_mpwrdlctl
= 0x36344038,
517 .p1_mpwrdlctl
= 0x422a423c,
520 /* microSOM with Solo processor and 512MB memory */
521 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib
= {
522 .p0_mpwldectrl0
= 0x0045004D,
523 .p0_mpwldectrl1
= 0x003A0047,
524 .p0_mpdgctrl0
= 0x023C0224,
525 .p0_mpdgctrl1
= 0x02000220,
526 .p0_mprddlctl
= 0x44444846,
527 .p0_mpwrdlctl
= 0x32343032,
530 /* microSOM with Dual lite processor and 1GB memory */
531 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib
= {
532 .p0_mpwldectrl0
= 0x0045004D,
533 .p0_mpwldectrl1
= 0x003A0047,
534 .p1_mpwldectrl0
= 0x001F001F,
535 .p1_mpwldectrl1
= 0x00210035,
536 .p0_mpdgctrl0
= 0x023C0224,
537 .p0_mpdgctrl1
= 0x02000220,
538 .p1_mpdgctrl0
= 0x02200220,
539 .p1_mpdgctrl1
= 0x02040208,
540 .p0_mprddlctl
= 0x44444846,
541 .p1_mprddlctl
= 0x4042463C,
542 .p0_mpwrdlctl
= 0x32343032,
543 .p1_mpwrdlctl
= 0x36363430,
546 static struct mx6_ddr3_cfg mem_ddr_2g
= {
560 static struct mx6_ddr3_cfg mem_ddr_4g
= {
573 static void ccgr_init(void)
575 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
577 writel(0x00C03F3F, &ccm
->CCGR0
);
578 writel(0x0030FC03, &ccm
->CCGR1
);
579 writel(0x0FFFC000, &ccm
->CCGR2
);
580 writel(0x3FF00000, &ccm
->CCGR3
);
581 writel(0x00FFF300, &ccm
->CCGR4
);
582 writel(0x0F0000C3, &ccm
->CCGR5
);
583 writel(0x000003FF, &ccm
->CCGR6
);
586 static void gpr_init(void)
588 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
590 /* enable AXI cache for VDOA/VPU/IPU */
591 writel(0xF00000CF, &iomux
->gpr
[4]);
592 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
593 writel(0x007F007F, &iomux
->gpr
[6]);
594 writel(0x007F007F, &iomux
->gpr
[7]);
598 * This section requires the differentiation between Solidrun mx6 boards, but
599 * for now, it will configure only for the mx6dual hummingboard version.
601 static void spl_dram_init(int width
)
603 struct mx6_ddr_sysinfo sysinfo
= {
604 /* width of data bus: 0=16, 1=32, 2=64 */
606 /* config for full 4GB range so that get_mem_size() works */
607 .cs_density
= 32, /* 32Gb per CS */
608 .ncs
= 1, /* single chip select */
610 .rtt_wr
= 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
611 .rtt_nom
= 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
612 .walat
= 1, /* Write additional latency */
613 .ralat
= 5, /* Read additional latency */
614 .mif3_mode
= 3, /* Command prediction working mode */
615 .bi_on
= 1, /* Bank interleaving enabled */
616 .sde_to_rst
= 0x10, /* 14 cycles, 200us (JEDEC default) */
617 .rst_to_cke
= 0x23, /* 33 cycles, 500us (JEDEC default) */
620 if (is_cpu_type(MXC_CPU_MX6D
) || is_cpu_type(MXC_CPU_MX6Q
))
621 mx6dq_dram_iocfg(width
, &mx6q_ddr_ioregs
, &mx6q_grp_ioregs
);
623 mx6sdl_dram_iocfg(width
, &mx6dl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
625 if (is_cpu_type(MXC_CPU_MX6D
))
626 mx6_dram_cfg(&sysinfo
, &mx6q_1g_mmcd_calib
, &mem_ddr_2g
);
627 else if (is_cpu_type(MXC_CPU_MX6Q
))
628 mx6_dram_cfg(&sysinfo
, &mx6q_2g_mmcd_calib
, &mem_ddr_4g
);
629 else if (is_cpu_type(MXC_CPU_MX6DL
))
630 mx6_dram_cfg(&sysinfo
, &mx6dl_1g_mmcd_calib
, &mem_ddr_2g
);
631 else if (is_cpu_type(MXC_CPU_MX6SOLO
))
632 mx6_dram_cfg(&sysinfo
, &mx6dl_512m_mmcd_calib
, &mem_ddr_2g
);
635 void board_init_f(ulong dummy
)
637 /* setup AIPS and disable watchdog */
643 /* iomux and setup of i2c */
644 board_early_init_f();
649 /* UART clocks enabled and gd valid - init serial console */
650 preloader_console_init();
652 /* DDR initialization */
653 if (is_cpu_type(MXC_CPU_MX6SOLO
))
659 memset(__bss_start
, 0, __bss_end
- __bss_start
);
661 /* load/boot image from boot device */
662 board_init_r(NULL
, 0);