board/spear/common/spr_lowlevel_init.S

   1 /*
   2  * (C) Copyright 2006
   3  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <config.h>
   9
  10 /*
  11  * platform specific initializations are already done in Xloader
  12  * Initializations already done include
  13  * DDR, PLLs, IP's clock enable and reset release etc
  14  */
  15 .globl lowlevel_init
  16 lowlevel_init:
  17         /* By default, U-Boot switches CPU to low-vector */
  18         /* Revert this as we work in high vector even in U-Boot */
  19         mrc     p15, 0, r0, c1, c0, 0
  20         orr     r0, r0, #0x00002000
  21         mcr     p15, 0, r0, c1, c0, 0
  22         mov     pc, lr
  23
  24 /* void setfreq(unsigned int device, unsigned int frequency) */
  25 .global setfreq
  26 setfreq:
  27         stmfd   sp!,{r14}
  28         stmfd   sp!,{r0-r12}
  29
  30         mov     r8,sp
  31         ldr     sp,SRAM_STACK_V
  32
  33         /* Saving the function arguements for later use */
  34         mov     r4,r0
  35         mov     r5,r1
  36
  37         /* Putting DDR into self refresh */
  38         ldr     r0,DDR_07_V
  39         ldr     r1,[r0]
  40         ldr     r2,DDR_ACTIVE_V
  41         bic     r1, r1, r2
  42         str     r1,[r0]
  43         ldr     r0,DDR_57_V
  44         ldr     r1,[r0]
  45         ldr     r2,CYCLES_MASK_V
  46         bic     r1, r1, r2
  47         ldr     r2,REFRESH_CYCLES_V
  48         orr     r1, r1, r2, lsl #16
  49         str     r1,[r0]
  50         ldr     r0,DDR_07_V
  51         ldr     r1,[r0]
  52         ldr     r2,SREFRESH_MASK_V
  53         orr     r1, r1, r2
  54         str     r1,[r0]
  55
  56         /* flush pipeline */
  57         b       flush
  58         .align 5
  59 flush:
  60         /* Delay to ensure self refresh mode */
  61         ldr     r0,SREFRESH_DELAY_V
  62 delay:
  63         sub     r0,r0,#1
  64         cmp     r0,#0
  65         bne     delay
  66
  67         /* Putting system in slow mode */
  68         ldr     r0,SCCTRL_V
  69         mov     r1,#2
  70         str     r1,[r0]
  71
  72         /* Changing PLL(1/2) frequency */
  73         mov     r0,r4
  74         mov     r1,r5
  75
  76         cmp     r4,#0
  77         beq     pll1_freq
  78
  79         /* Change PLL2 (DDR frequency) */
  80         ldr     r6,PLL2_FREQ_V
  81         ldr     r7,PLL2_CNTL_V
  82         b       pll2_freq
  83
  84 pll1_freq:
  85         /* Change PLL1 (CPU frequency) */
  86         ldr     r6,PLL1_FREQ_V
  87         ldr     r7,PLL1_CNTL_V
  88
  89 pll2_freq:
  90         mov     r0,r6
  91         ldr     r1,[r0]
  92         ldr     r2,PLLFREQ_MASK_V
  93         bic     r1,r1,r2
  94         mov     r2,r5,lsr#1
  95         orr     r1,r1,r2,lsl#24
  96         str     r1,[r0]
  97
  98         mov     r0,r7
  99         ldr     r1,P1C0A_V
 100         str     r1,[r0]
 101         ldr     r1,P1C0E_V
 102         str     r1,[r0]
 103         ldr     r1,P1C06_V
 104         str     r1,[r0]
 105         ldr     r1,P1C0E_V
 106         str     r1,[r0]
 107
 108 lock:
 109         ldr     r1,[r0]
 110         and     r1,r1,#1
 111         cmp     r1,#0
 112         beq     lock
 113
 114         /* Putting system back to normal mode */
 115         ldr     r0,SCCTRL_V
 116         mov     r1,#4
 117         str     r1,[r0]
 118
 119         /* Putting DDR back to normal */
 120         ldr     r0,DDR_07_V
 121         ldr     r1,[R0]
 122         ldr     r2,SREFRESH_MASK_V
 123         bic     r1, r1, r2
 124         str     r1,[r0]
 125         ldr     r2,DDR_ACTIVE_V
 126         orr     r1, r1, r2
 127         str     r1,[r0]
 128
 129         /* Delay to ensure self refresh mode */
 130         ldr     r0,SREFRESH_DELAY_V
 131 1:
 132         sub     r0,r0,#1
 133         cmp     r0,#0
 134         bne     1b
 135
 136         mov     sp,r8
 137         /* Resuming back to code */
 138         ldmia   sp!,{r0-r12}
 139         ldmia   sp!,{pc}
 140
 141 SCCTRL_V:
 142         .word 0xfca00000
 143 PLL1_FREQ_V:
 144         .word 0xfca8000C
 145 PLL1_CNTL_V:
 146         .word 0xfca80008
 147 PLL2_FREQ_V:
 148         .word 0xfca80018
 149 PLL2_CNTL_V:
 150         .word 0xfca80014
 151 PLLFREQ_MASK_V:
 152         .word 0xff000000
 153 P1C0A_V:
 154         .word 0x1C0A
 155 P1C0E_V:
 156         .word 0x1C0E
 157 P1C06_V:
 158         .word 0x1C06
 159
 160 SREFRESH_DELAY_V:
 161         .word 0x9999
 162 SRAM_STACK_V:
 163         .word 0xD2800600
 164 DDR_07_V:
 165         .word 0xfc60001c
 166 DDR_ACTIVE_V:
 167         .word 0x01000000
 168 DDR_57_V:
 169         .word 0xfc6000e4
 170 CYCLES_MASK_V:
 171         .word 0xffff0000
 172 REFRESH_CYCLES_V:
 173         .word 0xf0f0
 174 SREFRESH_MASK_V:
 175         .word 0x00010000
 176
 177 .global setfreq_sz
 178 setfreq_sz:
 179         .word setfreq_sz - setfreq