2 * (C) Copyright 2011, 2012, 2013
3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
4 * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
5 * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
6 * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
9 * Kamil Lulko, <kamil.lulko@gmail.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/armv7m.h>
17 #include <asm/arch/stm32.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/fmc.h>
20 #include <dm/platdata.h>
21 #include <dm/platform_data/serial_stm32.h>
22 #include <asm/arch/stm32_periph.h>
23 #include <asm/arch/stm32_defs.h>
25 DECLARE_GLOBAL_DATA_PTR
;
27 const struct stm32_gpio_ctl gpio_ctl_gpout
= {
28 .mode
= STM32_GPIO_MODE_OUT
,
29 .otype
= STM32_GPIO_OTYPE_PP
,
30 .speed
= STM32_GPIO_SPEED_50M
,
31 .pupd
= STM32_GPIO_PUPD_NO
,
35 const struct stm32_gpio_ctl gpio_ctl_usart
= {
36 .mode
= STM32_GPIO_MODE_AF
,
37 .otype
= STM32_GPIO_OTYPE_PP
,
38 .speed
= STM32_GPIO_SPEED_50M
,
39 .pupd
= STM32_GPIO_PUPD_UP
,
40 .af
= STM32_GPIO_USART
43 static const struct stm32_gpio_dsc usart_gpio
[] = {
44 {STM32_GPIO_PORT_X
, STM32_GPIO_PIN_TX
}, /* TX */
45 {STM32_GPIO_PORT_X
, STM32_GPIO_PIN_RX
}, /* RX */
48 int uart_setup_gpio(void)
53 for (i
= 0; i
< ARRAY_SIZE(usart_gpio
); i
++) {
54 rv
= stm32_gpio_config(&usart_gpio
[i
], &gpio_ctl_usart
);
63 const struct stm32_gpio_ctl gpio_ctl_fmc
= {
64 .mode
= STM32_GPIO_MODE_AF
,
65 .otype
= STM32_GPIO_OTYPE_PP
,
66 .speed
= STM32_GPIO_SPEED_100M
,
67 .pupd
= STM32_GPIO_PUPD_NO
,
71 static const struct stm32_gpio_dsc ext_ram_fmc_gpio
[] = {
72 /* Chip is LQFP144, see DM00077036.pdf for details */
73 {STM32_GPIO_PORT_D
, STM32_GPIO_PIN_10
}, /* 79, FMC_D15 */
74 {STM32_GPIO_PORT_D
, STM32_GPIO_PIN_9
}, /* 78, FMC_D14 */
75 {STM32_GPIO_PORT_D
, STM32_GPIO_PIN_8
}, /* 77, FMC_D13 */
76 {STM32_GPIO_PORT_E
, STM32_GPIO_PIN_15
}, /* 68, FMC_D12 */
77 {STM32_GPIO_PORT_E
, STM32_GPIO_PIN_14
}, /* 67, FMC_D11 */
78 {STM32_GPIO_PORT_E
, STM32_GPIO_PIN_13
}, /* 66, FMC_D10 */
79 {STM32_GPIO_PORT_E
, STM32_GPIO_PIN_12
}, /* 65, FMC_D9 */
80 {STM32_GPIO_PORT_E
, STM32_GPIO_PIN_11
}, /* 64, FMC_D8 */
81 {STM32_GPIO_PORT_E
, STM32_GPIO_PIN_10
}, /* 63, FMC_D7 */
82 {STM32_GPIO_PORT_E
, STM32_GPIO_PIN_9
}, /* 60, FMC_D6 */
83 {STM32_GPIO_PORT_E
, STM32_GPIO_PIN_8
}, /* 59, FMC_D5 */
84 {STM32_GPIO_PORT_E
, STM32_GPIO_PIN_7
}, /* 58, FMC_D4 */
85 {STM32_GPIO_PORT_D
, STM32_GPIO_PIN_1
}, /* 115, FMC_D3 */
86 {STM32_GPIO_PORT_D
, STM32_GPIO_PIN_0
}, /* 114, FMC_D2 */
87 {STM32_GPIO_PORT_D
, STM32_GPIO_PIN_15
}, /* 86, FMC_D1 */
88 {STM32_GPIO_PORT_D
, STM32_GPIO_PIN_14
}, /* 85, FMC_D0 */
89 {STM32_GPIO_PORT_E
, STM32_GPIO_PIN_1
}, /* 142, FMC_NBL1 */
90 {STM32_GPIO_PORT_E
, STM32_GPIO_PIN_0
}, /* 141, FMC_NBL0 */
91 {STM32_GPIO_PORT_G
, STM32_GPIO_PIN_5
}, /* 90, FMC_A15, BA1 */
92 {STM32_GPIO_PORT_G
, STM32_GPIO_PIN_4
}, /* 89, FMC_A14, BA0 */
93 {STM32_GPIO_PORT_G
, STM32_GPIO_PIN_1
}, /* 57, FMC_A11 */
94 {STM32_GPIO_PORT_G
, STM32_GPIO_PIN_0
}, /* 56, FMC_A10 */
95 {STM32_GPIO_PORT_F
, STM32_GPIO_PIN_15
}, /* 55, FMC_A9 */
96 {STM32_GPIO_PORT_F
, STM32_GPIO_PIN_14
}, /* 54, FMC_A8 */
97 {STM32_GPIO_PORT_F
, STM32_GPIO_PIN_13
}, /* 53, FMC_A7 */
98 {STM32_GPIO_PORT_F
, STM32_GPIO_PIN_12
}, /* 50, FMC_A6 */
99 {STM32_GPIO_PORT_F
, STM32_GPIO_PIN_5
}, /* 15, FMC_A5 */
100 {STM32_GPIO_PORT_F
, STM32_GPIO_PIN_4
}, /* 14, FMC_A4 */
101 {STM32_GPIO_PORT_F
, STM32_GPIO_PIN_3
}, /* 13, FMC_A3 */
102 {STM32_GPIO_PORT_F
, STM32_GPIO_PIN_2
}, /* 12, FMC_A2 */
103 {STM32_GPIO_PORT_F
, STM32_GPIO_PIN_1
}, /* 11, FMC_A1 */
104 {STM32_GPIO_PORT_F
, STM32_GPIO_PIN_0
}, /* 10, FMC_A0 */
105 {STM32_GPIO_PORT_B
, STM32_GPIO_PIN_6
}, /* 136, SDRAM_NE */
106 {STM32_GPIO_PORT_F
, STM32_GPIO_PIN_11
}, /* 49, SDRAM_NRAS */
107 {STM32_GPIO_PORT_G
, STM32_GPIO_PIN_15
}, /* 132, SDRAM_NCAS */
108 {STM32_GPIO_PORT_C
, STM32_GPIO_PIN_0
}, /* 26, SDRAM_NWE */
109 {STM32_GPIO_PORT_B
, STM32_GPIO_PIN_5
}, /* 135, SDRAM_CKE */
110 {STM32_GPIO_PORT_G
, STM32_GPIO_PIN_8
}, /* 93, SDRAM_CLK */
113 static int fmc_setup_gpio(void)
118 for (i
= 0; i
< ARRAY_SIZE(ext_ram_fmc_gpio
); i
++) {
119 rv
= stm32_gpio_config(&ext_ram_fmc_gpio
[i
],
130 * STM32 RCC FMC specific definitions
132 #define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */
134 static inline u32
_ns2clk(u32 ns
, u32 freq
)
136 u32 tmp
= freq
/1000000;
137 return (tmp
* ns
) / 1000;
140 #define NS2CLK(ns) (_ns2clk(ns, freq))
143 * Following are timings for IS42S16400J, from corresponding datasheet
145 #define SDRAM_CAS 3 /* 3 cycles */
146 #define SDRAM_NB 1 /* Number of banks */
147 #define SDRAM_MWID 1 /* 16 bit memory */
149 #define SDRAM_NR 0x1 /* 12-bit row */
150 #define SDRAM_NC 0x0 /* 8-bit col */
151 #define SDRAM_RBURST 0x1 /* Single read requests always as bursts */
152 #define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */
154 #define SDRAM_TRRD (NS2CLK(14) - 1)
155 #define SDRAM_TRCD (NS2CLK(15) - 1)
156 #define SDRAM_TRP (NS2CLK(15) - 1)
157 #define SDRAM_TRAS (NS2CLK(42) - 1)
158 #define SDRAM_TRC (NS2CLK(63) - 1)
159 #define SDRAM_TRFC (NS2CLK(63) - 1)
160 #define SDRAM_TCDL (1 - 1)
161 #define SDRAM_TRDL (2 - 1)
162 #define SDRAM_TBDL (1 - 1)
163 #define SDRAM_TREF 1386
164 #define SDRAM_TCCD (1 - 1)
166 #define SDRAM_TXSR (NS2CLK(70) - 1)/* Row cycle time after precharge */
167 #define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */
169 /* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */
170 #define SDRAM_TWR max(\
171 (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \
172 (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\
175 #define SDRAM_MODE_BL_SHIFT 0
176 #define SDRAM_MODE_CAS_SHIFT 4
177 #define SDRAM_MODE_BL 0
178 #define SDRAM_MODE_CAS SDRAM_CAS
185 rv
= fmc_setup_gpio();
189 setbits_le32(&STM32_RCC
->ahb3enr
, STM32_RCC_ENR_FMC
);
192 * Get frequency for NS2CLK calculation.
194 freq
= clock_get(CLOCK_AHB
) / CONFIG_SYS_RAM_FREQ_DIV
;
196 writel(CONFIG_SYS_RAM_FREQ_DIV
<< FMC_SDCR_SDCLK_SHIFT
197 | SDRAM_RPIPE
<< FMC_SDCR_RPIPE_SHIFT
198 | SDRAM_RBURST
<< FMC_SDCR_RBURST_SHIFT
,
199 &STM32_SDRAM_FMC
->sdcr1
);
201 writel(CONFIG_SYS_RAM_FREQ_DIV
<< FMC_SDCR_SDCLK_SHIFT
202 | SDRAM_CAS
<< FMC_SDCR_CAS_SHIFT
203 | SDRAM_NB
<< FMC_SDCR_NB_SHIFT
204 | SDRAM_MWID
<< FMC_SDCR_MWID_SHIFT
205 | SDRAM_NR
<< FMC_SDCR_NR_SHIFT
206 | SDRAM_NC
<< FMC_SDCR_NC_SHIFT
207 | SDRAM_RPIPE
<< FMC_SDCR_RPIPE_SHIFT
208 | SDRAM_RBURST
<< FMC_SDCR_RBURST_SHIFT
,
209 &STM32_SDRAM_FMC
->sdcr2
);
211 writel(SDRAM_TRP
<< FMC_SDTR_TRP_SHIFT
212 | SDRAM_TRC
<< FMC_SDTR_TRC_SHIFT
,
213 &STM32_SDRAM_FMC
->sdtr1
);
215 writel(SDRAM_TRCD
<< FMC_SDTR_TRCD_SHIFT
216 | SDRAM_TRP
<< FMC_SDTR_TRP_SHIFT
217 | SDRAM_TWR
<< FMC_SDTR_TWR_SHIFT
218 | SDRAM_TRC
<< FMC_SDTR_TRC_SHIFT
219 | SDRAM_TRAS
<< FMC_SDTR_TRAS_SHIFT
220 | SDRAM_TXSR
<< FMC_SDTR_TXSR_SHIFT
221 | SDRAM_TMRD
<< FMC_SDTR_TMRD_SHIFT
,
222 &STM32_SDRAM_FMC
->sdtr2
);
224 writel(FMC_SDCMR_BANK_2
| FMC_SDCMR_MODE_START_CLOCK
,
225 &STM32_SDRAM_FMC
->sdcmr
);
227 udelay(200); /* 200 us delay, page 10, "Power-Up" */
230 writel(FMC_SDCMR_BANK_2
| FMC_SDCMR_MODE_PRECHARGE
,
231 &STM32_SDRAM_FMC
->sdcmr
);
236 writel((FMC_SDCMR_BANK_2
| FMC_SDCMR_MODE_AUTOREFRESH
237 | 7 << FMC_SDCMR_NRFS_SHIFT
), &STM32_SDRAM_FMC
->sdcmr
);
242 writel(FMC_SDCMR_BANK_2
| (SDRAM_MODE_BL
<< SDRAM_MODE_BL_SHIFT
243 | SDRAM_MODE_CAS
<< SDRAM_MODE_CAS_SHIFT
)
244 << FMC_SDCMR_MODE_REGISTER_SHIFT
| FMC_SDCMR_MODE_WRITE_MODE
,
245 &STM32_SDRAM_FMC
->sdcmr
);
251 writel(FMC_SDCMR_BANK_2
| FMC_SDCMR_MODE_NORMAL
,
252 &STM32_SDRAM_FMC
->sdcmr
);
257 writel(SDRAM_TREF
, &STM32_SDRAM_FMC
->sdrtr
);
260 * Fill in global info with description of SRAM configuration
262 gd
->bd
->bi_dram
[0].start
= CONFIG_SYS_RAM_BASE
;
263 gd
->bd
->bi_dram
[0].size
= CONFIG_SYS_RAM_SIZE
;
265 gd
->ram_size
= CONFIG_SYS_RAM_SIZE
;
270 static const struct stm32_serial_platdata serial_platdata
= {
271 .base
= (struct stm32_usart
*)STM32_USART1_BASE
,
274 U_BOOT_DEVICE(stm32_serials
) = {
275 .name
= "serial_stm32",
276 .platdata
= &serial_platdata
,
279 u32
get_board_rev(void)
284 int board_early_init_f(void)
288 res
= uart_setup_gpio();
291 clock_setup(USART1_CLOCK_CFG
);
298 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
303 #ifdef CONFIG_MISC_INIT_R
304 int misc_init_r(void)
307 uint32_t u_id_low
, u_id_mid
, u_id_high
;
309 if (!getenv("serial#")) {
310 u_id_low
= readl(&STM32_U_ID
->u_id_low
);
311 u_id_mid
= readl(&STM32_U_ID
->u_id_mid
);
312 u_id_high
= readl(&STM32_U_ID
->u_id_high
);
313 sprintf(serialno
, "%08x%08x%08x",
314 u_id_high
, u_id_mid
, u_id_low
);
315 setenv("serial#", serialno
);