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[people/ms/u-boot.git] / board / ti / am43xx / board.c
1 /*
2 * board.c
3 *
4 * Board functions for TI AM43XX based boards
5 *
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <common.h>
12 #include <i2c.h>
13 #include <asm/errno.h>
14 #include <spl.h>
15 #include <usb.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/mux.h>
19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/emif.h>
22 #include "board.h"
23 #include <power/pmic.h>
24 #include <power/tps65218.h>
25 #include <power/tps62362.h>
26 #include <miiphy.h>
27 #include <cpsw.h>
28 #include <linux/usb/gadget.h>
29 #include <dwc3-uboot.h>
30 #include <dwc3-omap-uboot.h>
31 #include <ti-usb-phy-uboot.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
36
37 /*
38 * Read header information from EEPROM into global structure.
39 */
40 static int read_eeprom(struct am43xx_board_id *header)
41 {
42 /* Check if baseboard eeprom is available */
43 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
44 printf("Could not probe the EEPROM at 0x%x\n",
45 CONFIG_SYS_I2C_EEPROM_ADDR);
46 return -ENODEV;
47 }
48
49 /* read the eeprom using i2c */
50 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
51 sizeof(struct am43xx_board_id))) {
52 printf("Could not read the EEPROM\n");
53 return -EIO;
54 }
55
56 if (header->magic != 0xEE3355AA) {
57 /*
58 * read the eeprom using i2c again,
59 * but use only a 1 byte address
60 */
61 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
62 sizeof(struct am43xx_board_id))) {
63 printf("Could not read the EEPROM at 0x%x\n",
64 CONFIG_SYS_I2C_EEPROM_ADDR);
65 return -EIO;
66 }
67
68 if (header->magic != 0xEE3355AA) {
69 printf("Incorrect magic number (0x%x) in EEPROM\n",
70 header->magic);
71 return -EINVAL;
72 }
73 }
74
75 strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
76 am43xx_board_name[sizeof(header->name)] = 0;
77
78 strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
79 am43xx_board_rev[sizeof(header->version)] = 0;
80
81 return 0;
82 }
83
84 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
85
86 #define NUM_OPPS 6
87
88 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
89 { /* 19.2 MHz */
90 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
91 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
92 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
93 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
94 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
95 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
96 },
97 { /* 24 MHz */
98 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
99 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
100 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
101 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
102 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
103 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
104 },
105 { /* 25 MHz */
106 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
107 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
108 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
109 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
110 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
111 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
112 },
113 { /* 26 MHz */
114 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
115 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
116 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
117 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
118 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
119 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
120 },
121 };
122
123 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
124 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
125 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
126 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
127 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
128 };
129
130 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
131 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
132 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
133 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
134 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
135 };
136
137 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
138 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
139 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
140 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
141 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
142 };
143
144 const struct dpll_params gp_evm_dpll_ddr = {
145 50, 2, 1, -1, 2, -1, -1};
146
147 static const struct dpll_params idk_dpll_ddr = {
148 400, 23, 1, -1, 2, -1, -1
149 };
150
151 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
152 0x00500050,
153 0x00350035,
154 0x00350035,
155 0x00350035,
156 0x00350035,
157 0x00350035,
158 0x00000000,
159 0x00000000,
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000000,
164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x40001000,
171 0x08102040
172 };
173
174 const struct ctrl_ioregs ioregs_lpddr2 = {
175 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
176 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
177 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
178 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
179 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
180 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
181 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
182 .emif_sdram_config_ext = 0x1,
183 };
184
185 const struct emif_regs emif_regs_lpddr2 = {
186 .sdram_config = 0x808012BA,
187 .ref_ctrl = 0x0000040D,
188 .sdram_tim1 = 0xEA86B411,
189 .sdram_tim2 = 0x103A094A,
190 .sdram_tim3 = 0x0F6BA37F,
191 .read_idle_ctrl = 0x00050000,
192 .zq_config = 0x50074BE4,
193 .temp_alert_config = 0x0,
194 .emif_rd_wr_lvl_rmp_win = 0x0,
195 .emif_rd_wr_lvl_rmp_ctl = 0x0,
196 .emif_rd_wr_lvl_ctl = 0x0,
197 .emif_ddr_phy_ctlr_1 = 0x0E284006,
198 .emif_rd_wr_exec_thresh = 0x80000405,
199 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
200 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
201 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
202 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
203 .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
204 .emif_prio_class_serv_map = 0x80000001,
205 .emif_connect_id_serv_1_map = 0x80000094,
206 .emif_connect_id_serv_2_map = 0x00000000,
207 .emif_cos_config = 0x000FFFFF
208 };
209
210 const struct ctrl_ioregs ioregs_ddr3 = {
211 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
212 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
213 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
214 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
215 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
216 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
217 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
218 .emif_sdram_config_ext = 0xc163,
219 };
220
221 const struct emif_regs ddr3_emif_regs_400Mhz = {
222 .sdram_config = 0x638413B2,
223 .ref_ctrl = 0x00000C30,
224 .sdram_tim1 = 0xEAAAD4DB,
225 .sdram_tim2 = 0x266B7FDA,
226 .sdram_tim3 = 0x107F8678,
227 .read_idle_ctrl = 0x00050000,
228 .zq_config = 0x50074BE4,
229 .temp_alert_config = 0x0,
230 .emif_ddr_phy_ctlr_1 = 0x0E004008,
231 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
232 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
233 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
234 .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
235 .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
236 .emif_rd_wr_lvl_rmp_win = 0x0,
237 .emif_rd_wr_lvl_rmp_ctl = 0x0,
238 .emif_rd_wr_lvl_ctl = 0x0,
239 .emif_rd_wr_exec_thresh = 0x80000405,
240 .emif_prio_class_serv_map = 0x80000001,
241 .emif_connect_id_serv_1_map = 0x80000094,
242 .emif_connect_id_serv_2_map = 0x00000000,
243 .emif_cos_config = 0x000FFFFF
244 };
245
246 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
247 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
248 .sdram_config = 0x638413B2,
249 .ref_ctrl = 0x00000C30,
250 .sdram_tim1 = 0xEAAAD4DB,
251 .sdram_tim2 = 0x266B7FDA,
252 .sdram_tim3 = 0x107F8678,
253 .read_idle_ctrl = 0x00050000,
254 .zq_config = 0x50074BE4,
255 .temp_alert_config = 0x0,
256 .emif_ddr_phy_ctlr_1 = 0x0E004008,
257 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
258 .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
259 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
260 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
261 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
262 .emif_rd_wr_exec_thresh = 0x80000405,
263 .emif_prio_class_serv_map = 0x80000001,
264 .emif_connect_id_serv_1_map = 0x80000094,
265 .emif_connect_id_serv_2_map = 0x00000000,
266 .emif_cos_config = 0x000FFFFF
267 };
268
269 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
270 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
271 .sdram_config = 0x638413B2,
272 .ref_ctrl = 0x00000C30,
273 .sdram_tim1 = 0xEAAAD4DB,
274 .sdram_tim2 = 0x266B7FDA,
275 .sdram_tim3 = 0x107F8678,
276 .read_idle_ctrl = 0x00050000,
277 .zq_config = 0x50074BE4,
278 .temp_alert_config = 0x0,
279 .emif_ddr_phy_ctlr_1 = 0x0E004008,
280 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
281 .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
282 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
283 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
284 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
285 .emif_rd_wr_exec_thresh = 0x80000405,
286 .emif_prio_class_serv_map = 0x80000001,
287 .emif_connect_id_serv_1_map = 0x80000094,
288 .emif_connect_id_serv_2_map = 0x00000000,
289 .emif_cos_config = 0x000FFFFF
290 };
291
292 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
293 .sdram_config = 0x638413b2,
294 .sdram_config2 = 0x00000000,
295 .ref_ctrl = 0x00000c30,
296 .sdram_tim1 = 0xeaaad4db,
297 .sdram_tim2 = 0x266b7fda,
298 .sdram_tim3 = 0x107f8678,
299 .read_idle_ctrl = 0x00050000,
300 .zq_config = 0x50074be4,
301 .temp_alert_config = 0x0,
302 .emif_ddr_phy_ctlr_1 = 0x0e084008,
303 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
304 .emif_ddr_ext_phy_ctrl_2 = 0x89,
305 .emif_ddr_ext_phy_ctrl_3 = 0x90,
306 .emif_ddr_ext_phy_ctrl_4 = 0x8e,
307 .emif_ddr_ext_phy_ctrl_5 = 0x8d,
308 .emif_rd_wr_lvl_rmp_win = 0x0,
309 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
310 .emif_rd_wr_lvl_ctl = 0x00000000,
311 .emif_rd_wr_exec_thresh = 0x80000000,
312 .emif_prio_class_serv_map = 0x80000001,
313 .emif_connect_id_serv_1_map = 0x80000094,
314 .emif_connect_id_serv_2_map = 0x00000000,
315 .emif_cos_config = 0x000FFFFF
316 };
317
318 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
319 .sdram_config = 0x61a11b32,
320 .sdram_config2 = 0x00000000,
321 .ref_ctrl = 0x00000c30,
322 .sdram_tim1 = 0xeaaad4db,
323 .sdram_tim2 = 0x266b7fda,
324 .sdram_tim3 = 0x107f8678,
325 .read_idle_ctrl = 0x00050000,
326 .zq_config = 0x50074be4,
327 .temp_alert_config = 0x00000000,
328 .emif_ddr_phy_ctlr_1 = 0x00008009,
329 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
330 .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
331 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
332 .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
333 .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
334 .emif_rd_wr_lvl_rmp_win = 0x00000000,
335 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
336 .emif_rd_wr_lvl_ctl = 0x00000000,
337 .emif_rd_wr_exec_thresh = 0x00000405,
338 .emif_prio_class_serv_map = 0x00000000,
339 .emif_connect_id_serv_1_map = 0x00000000,
340 .emif_connect_id_serv_2_map = 0x00000000,
341 .emif_cos_config = 0x00ffffff
342 };
343
344 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
345 {
346 if (board_is_eposevm()) {
347 *regs = ext_phy_ctrl_const_base_lpddr2;
348 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
349 }
350
351 return;
352 }
353
354 /*
355 * get_sys_clk_index : returns the index of the sys_clk read from
356 * ctrl status register. This value is either
357 * read from efuse or sysboot pins.
358 */
359 static u32 get_sys_clk_index(void)
360 {
361 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
362 u32 ind = readl(&ctrl->statusreg), src;
363
364 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
365 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
366 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
367 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
368 else /* Value read from SYS BOOT pins */
369 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
370 CTRL_SYSBOOT_15_14_SHIFT);
371 }
372
373 const struct dpll_params *get_dpll_ddr_params(void)
374 {
375 int ind = get_sys_clk_index();
376
377 if (board_is_eposevm())
378 return &epos_evm_dpll_ddr[ind];
379 else if (board_is_gpevm() || board_is_sk())
380 return &gp_evm_dpll_ddr;
381 else if (board_is_idk())
382 return &idk_dpll_ddr;
383
384 printf(" Board '%s' not supported\n", am43xx_board_name);
385 return NULL;
386 }
387
388
389 /*
390 * get_opp_offset:
391 * Returns the index for safest OPP of the device to boot.
392 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
393 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
394 * This data is read from dev_attribute register which is e-fused.
395 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
396 * OPP available. Lowest OPP starts with min_off. So returning the
397 * bit with rightmost '0'.
398 */
399 static int get_opp_offset(int max_off, int min_off)
400 {
401 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
402 int opp, offset, i;
403
404 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
405 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
406
407 for (i = max_off; i >= min_off; i--) {
408 offset = opp & (1 << i);
409 if (!offset)
410 return i;
411 }
412
413 return min_off;
414 }
415
416 const struct dpll_params *get_dpll_mpu_params(void)
417 {
418 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
419 u32 ind = get_sys_clk_index();
420
421 return &dpll_mpu[ind][opp];
422 }
423
424 const struct dpll_params *get_dpll_core_params(void)
425 {
426 int ind = get_sys_clk_index();
427
428 return &dpll_core[ind];
429 }
430
431 const struct dpll_params *get_dpll_per_params(void)
432 {
433 int ind = get_sys_clk_index();
434
435 return &dpll_per[ind];
436 }
437
438 void scale_vcores_generic(u32 m)
439 {
440 int mpu_vdd;
441
442 if (i2c_probe(TPS65218_CHIP_PM))
443 return;
444
445 switch (m) {
446 case 1000:
447 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
448 break;
449 case 800:
450 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
451 break;
452 case 720:
453 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
454 break;
455 case 600:
456 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
457 break;
458 case 300:
459 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
460 break;
461 default:
462 puts("Unknown MPU clock, not scaling\n");
463 return;
464 }
465
466 /* Set DCDC1 (CORE) voltage to 1.1V */
467 if (tps65218_voltage_update(TPS65218_DCDC1,
468 TPS65218_DCDC_VOLT_SEL_1100MV)) {
469 printf("%s failure\n", __func__);
470 return;
471 }
472
473 /* Set DCDC2 (MPU) voltage */
474 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
475 printf("%s failure\n", __func__);
476 return;
477 }
478 }
479
480 void scale_vcores_idk(u32 m)
481 {
482 int mpu_vdd;
483
484 if (i2c_probe(TPS62362_I2C_ADDR))
485 return;
486
487 switch (m) {
488 case 1000:
489 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
490 break;
491 case 800:
492 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
493 break;
494 case 720:
495 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
496 break;
497 case 600:
498 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
499 break;
500 case 300:
501 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
502 break;
503 default:
504 puts("Unknown MPU clock, not scaling\n");
505 return;
506 }
507
508 /* Set VDD_MPU voltage */
509 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
510 printf("%s failure\n", __func__);
511 return;
512 }
513 }
514
515 void scale_vcores(void)
516 {
517 const struct dpll_params *mpu_params;
518 struct am43xx_board_id header;
519
520 enable_i2c0_pin_mux();
521 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
522 if (read_eeprom(&header) < 0)
523 puts("Could not get board ID.\n");
524
525 /* Get the frequency */
526 mpu_params = get_dpll_mpu_params();
527
528 if (board_is_idk())
529 scale_vcores_idk(mpu_params->m);
530 else
531 scale_vcores_generic(mpu_params->m);
532 }
533
534 void set_uart_mux_conf(void)
535 {
536 enable_uart0_pin_mux();
537 }
538
539 void set_mux_conf_regs(void)
540 {
541 enable_board_pin_mux();
542 }
543
544 static void enable_vtt_regulator(void)
545 {
546 u32 temp;
547
548 /* enable module */
549 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
550
551 /* enable output for GPIO5_7 */
552 writel(GPIO_SETDATAOUT(7),
553 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
554 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
555 temp = temp & ~(GPIO_OE_ENABLE(7));
556 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
557 }
558
559 void sdram_init(void)
560 {
561 /*
562 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
563 * GP EMV has 1GB DDR3 connected to EMIF
564 * along with VTT regulator.
565 */
566 if (board_is_eposevm()) {
567 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
568 } else if (board_is_evm_14_or_later()) {
569 enable_vtt_regulator();
570 config_ddr(0, &ioregs_ddr3, NULL, NULL,
571 &ddr3_emif_regs_400Mhz_production, 0);
572 } else if (board_is_evm_12_or_later()) {
573 enable_vtt_regulator();
574 config_ddr(0, &ioregs_ddr3, NULL, NULL,
575 &ddr3_emif_regs_400Mhz_beta, 0);
576 } else if (board_is_gpevm()) {
577 enable_vtt_regulator();
578 config_ddr(0, &ioregs_ddr3, NULL, NULL,
579 &ddr3_emif_regs_400Mhz, 0);
580 } else if (board_is_sk()) {
581 config_ddr(400, &ioregs_ddr3, NULL, NULL,
582 &ddr3_sk_emif_regs_400Mhz, 0);
583 } else if (board_is_idk()) {
584 config_ddr(400, &ioregs_ddr3, NULL, NULL,
585 &ddr3_idk_emif_regs_400Mhz, 0);
586 }
587 }
588 #endif
589
590 /* setup board specific PMIC */
591 int power_init_board(void)
592 {
593 struct pmic *p;
594
595 if (board_is_idk()) {
596 power_tps62362_init(I2C_PMIC);
597 p = pmic_get("TPS62362");
598 if (p && !pmic_probe(p))
599 puts("PMIC: TPS62362\n");
600 } else {
601 power_tps65218_init(I2C_PMIC);
602 p = pmic_get("TPS65218_PMIC");
603 if (p && !pmic_probe(p))
604 puts("PMIC: TPS65218\n");
605 }
606
607 return 0;
608 }
609
610 int board_init(void)
611 {
612 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
613 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
614 modena_init0_bw_integer, modena_init0_watermark_0;
615
616 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
617 gpmc_init();
618
619 /* Clear all important bits for DSS errata that may need to be tweaked*/
620 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
621 MREQPRIO_0_SAB_INIT0_MASK;
622
623 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
624
625 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
626 BW_LIMITER_BW_FRAC_MASK;
627
628 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
629 BW_LIMITER_BW_INT_MASK;
630
631 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
632 BW_LIMITER_BW_WATERMARK_MASK;
633
634 /* Setting MReq Priority of the DSS*/
635 mreqprio_0 |= 0x77;
636
637 /*
638 * Set L3 Fast Configuration Register
639 * Limiting bandwith for ARM core to 700 MBPS
640 */
641 modena_init0_bw_fractional |= 0x10;
642 modena_init0_bw_integer |= 0x3;
643
644 writel(mreqprio_0, &cdev->mreqprio_0);
645 writel(mreqprio_1, &cdev->mreqprio_1);
646
647 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
648 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
649 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
650
651 return 0;
652 }
653
654 #ifdef CONFIG_BOARD_LATE_INIT
655 int board_late_init(void)
656 {
657 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
658 char safe_string[HDR_NAME_LEN + 1];
659 struct am43xx_board_id header;
660
661 if (read_eeprom(&header) < 0)
662 puts("Could not get board ID.\n");
663
664 /* Now set variables based on the header. */
665 strncpy(safe_string, (char *)header.name, sizeof(header.name));
666 safe_string[sizeof(header.name)] = 0;
667 setenv("board_name", safe_string);
668
669 strncpy(safe_string, (char *)header.version, sizeof(header.version));
670 safe_string[sizeof(header.version)] = 0;
671 setenv("board_rev", safe_string);
672 #endif
673 return 0;
674 }
675 #endif
676
677 #ifdef CONFIG_USB_DWC3
678 static struct dwc3_device usb_otg_ss1 = {
679 .maximum_speed = USB_SPEED_HIGH,
680 .base = USB_OTG_SS1_BASE,
681 .tx_fifo_resize = false,
682 .index = 0,
683 };
684
685 static struct dwc3_omap_device usb_otg_ss1_glue = {
686 .base = (void *)USB_OTG_SS1_GLUE_BASE,
687 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
688 .vbus_id_status = OMAP_DWC3_VBUS_VALID,
689 .index = 0,
690 };
691
692 static struct ti_usb_phy_device usb_phy1_device = {
693 .usb2_phy_power = (void *)USB2_PHY1_POWER,
694 .index = 0,
695 };
696
697 static struct dwc3_device usb_otg_ss2 = {
698 .maximum_speed = USB_SPEED_HIGH,
699 .base = USB_OTG_SS2_BASE,
700 .tx_fifo_resize = false,
701 .index = 1,
702 };
703
704 static struct dwc3_omap_device usb_otg_ss2_glue = {
705 .base = (void *)USB_OTG_SS2_GLUE_BASE,
706 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
707 .vbus_id_status = OMAP_DWC3_VBUS_VALID,
708 .index = 1,
709 };
710
711 static struct ti_usb_phy_device usb_phy2_device = {
712 .usb2_phy_power = (void *)USB2_PHY2_POWER,
713 .index = 1,
714 };
715
716 int board_usb_init(int index, enum usb_init_type init)
717 {
718 switch (index) {
719 case 0:
720 if (init == USB_INIT_DEVICE) {
721 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
722 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
723 } else {
724 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
725 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
726 }
727
728 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
729 ti_usb_phy_uboot_init(&usb_phy1_device);
730 dwc3_uboot_init(&usb_otg_ss1);
731 break;
732 case 1:
733 if (init == USB_INIT_DEVICE) {
734 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
735 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
736 } else {
737 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
738 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
739 }
740
741 ti_usb_phy_uboot_init(&usb_phy2_device);
742 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
743 dwc3_uboot_init(&usb_otg_ss2);
744 break;
745 default:
746 printf("Invalid Controller Index\n");
747 }
748
749 return 0;
750 }
751
752 int board_usb_cleanup(int index, enum usb_init_type init)
753 {
754 switch (index) {
755 case 0:
756 case 1:
757 ti_usb_phy_uboot_exit(index);
758 dwc3_uboot_exit(index);
759 dwc3_omap_uboot_exit(index);
760 break;
761 default:
762 printf("Invalid Controller Index\n");
763 }
764
765 return 0;
766 }
767
768 int usb_gadget_handle_interrupts(int index)
769 {
770 u32 status;
771
772 status = dwc3_omap_uboot_interrupt_status(index);
773 if (status)
774 dwc3_uboot_handle_interrupt(index);
775
776 return 0;
777 }
778 #endif
779
780 #ifdef CONFIG_DRIVER_TI_CPSW
781
782 static void cpsw_control(int enabled)
783 {
784 /* Additional controls can be added here */
785 return;
786 }
787
788 static struct cpsw_slave_data cpsw_slaves[] = {
789 {
790 .slave_reg_ofs = 0x208,
791 .sliver_reg_ofs = 0xd80,
792 .phy_addr = 16,
793 },
794 {
795 .slave_reg_ofs = 0x308,
796 .sliver_reg_ofs = 0xdc0,
797 .phy_addr = 1,
798 },
799 };
800
801 static struct cpsw_platform_data cpsw_data = {
802 .mdio_base = CPSW_MDIO_BASE,
803 .cpsw_base = CPSW_BASE,
804 .mdio_div = 0xff,
805 .channels = 8,
806 .cpdma_reg_ofs = 0x800,
807 .slaves = 1,
808 .slave_data = cpsw_slaves,
809 .ale_reg_ofs = 0xd00,
810 .ale_entries = 1024,
811 .host_port_reg_ofs = 0x108,
812 .hw_stats_reg_ofs = 0x900,
813 .bd_ram_ofs = 0x2000,
814 .mac_control = (1 << 5),
815 .control = cpsw_control,
816 .host_port_num = 0,
817 .version = CPSW_CTRL_VERSION_2,
818 };
819
820 int board_eth_init(bd_t *bis)
821 {
822 int rv;
823 uint8_t mac_addr[6];
824 uint32_t mac_hi, mac_lo;
825
826 /* try reading mac address from efuse */
827 mac_lo = readl(&cdev->macid0l);
828 mac_hi = readl(&cdev->macid0h);
829 mac_addr[0] = mac_hi & 0xFF;
830 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
831 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
832 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
833 mac_addr[4] = mac_lo & 0xFF;
834 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
835
836 if (!getenv("ethaddr")) {
837 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
838 if (is_valid_ethaddr(mac_addr))
839 eth_setenv_enetaddr("ethaddr", mac_addr);
840 }
841
842 mac_lo = readl(&cdev->macid1l);
843 mac_hi = readl(&cdev->macid1h);
844 mac_addr[0] = mac_hi & 0xFF;
845 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
846 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
847 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
848 mac_addr[4] = mac_lo & 0xFF;
849 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
850
851 if (!getenv("eth1addr")) {
852 if (is_valid_ethaddr(mac_addr))
853 eth_setenv_enetaddr("eth1addr", mac_addr);
854 }
855
856 if (board_is_eposevm()) {
857 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
858 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
859 cpsw_slaves[0].phy_addr = 16;
860 } else if (board_is_sk()) {
861 writel(RGMII_MODE_ENABLE, &cdev->miisel);
862 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
863 cpsw_slaves[0].phy_addr = 4;
864 cpsw_slaves[1].phy_addr = 5;
865 } else if (board_is_idk()) {
866 writel(RGMII_MODE_ENABLE, &cdev->miisel);
867 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
868 cpsw_slaves[0].phy_addr = 0;
869 } else {
870 writel(RGMII_MODE_ENABLE, &cdev->miisel);
871 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
872 cpsw_slaves[0].phy_addr = 0;
873 }
874
875 rv = cpsw_register(&cpsw_data);
876 if (rv < 0)
877 printf("Error %d registering CPSW switch\n", rv);
878
879 return rv;
880 }
881 #endif
"Das U-Boot" Source Tree