4 * Board functions for TI AM43XX based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/mux.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/gpio.h>
22 #include <power/pmic.h>
23 #include <power/tps65218.h>
24 #include <power/tps62362.h>
28 DECLARE_GLOBAL_DATA_PTR
;
30 static struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
33 * Read header information from EEPROM into global structure.
35 static int read_eeprom(struct am43xx_board_id
*header
)
37 /* Check if baseboard eeprom is available */
38 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR
)) {
39 printf("Could not probe the EEPROM at 0x%x\n",
40 CONFIG_SYS_I2C_EEPROM_ADDR
);
44 /* read the eeprom using i2c */
45 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR
, 0, 2, (uchar
*)header
,
46 sizeof(struct am43xx_board_id
))) {
47 printf("Could not read the EEPROM\n");
51 if (header
->magic
!= 0xEE3355AA) {
53 * read the eeprom using i2c again,
54 * but use only a 1 byte address
56 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR
, 0, 1, (uchar
*)header
,
57 sizeof(struct am43xx_board_id
))) {
58 printf("Could not read the EEPROM at 0x%x\n",
59 CONFIG_SYS_I2C_EEPROM_ADDR
);
63 if (header
->magic
!= 0xEE3355AA) {
64 printf("Incorrect magic number (0x%x) in EEPROM\n",
70 strncpy(am43xx_board_name
, (char *)header
->name
, sizeof(header
->name
));
71 am43xx_board_name
[sizeof(header
->name
)] = 0;
73 strncpy(am43xx_board_rev
, (char *)header
->version
, sizeof(header
->version
));
74 am43xx_board_rev
[sizeof(header
->version
)] = 0;
79 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
83 const struct dpll_params dpll_mpu
[NUM_CRYSTAL_FREQ
][NUM_OPPS
] = {
85 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
86 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
87 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
88 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
89 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
90 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
93 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
94 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
95 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
96 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
97 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
98 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
101 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
102 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
103 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
104 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
105 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
106 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
109 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
110 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
111 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
112 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
113 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
114 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
118 const struct dpll_params dpll_core
[NUM_CRYSTAL_FREQ
] = {
119 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
120 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
121 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
122 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
125 const struct dpll_params dpll_per
[NUM_CRYSTAL_FREQ
] = {
126 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
127 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
128 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
129 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
132 const struct dpll_params epos_evm_dpll_ddr
[NUM_CRYSTAL_FREQ
] = {
133 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
134 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
135 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
136 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
139 const struct dpll_params gp_evm_dpll_ddr
= {
140 50, 2, 1, -1, 2, -1, -1};
142 static const struct dpll_params idk_dpll_ddr
= {
143 400, 23, 1, -1, 2, -1, -1
146 const struct ctrl_ioregs ioregs_lpddr2
= {
147 .cm0ioctl
= LPDDR2_ADDRCTRL_IOCTRL_VALUE
,
148 .cm1ioctl
= LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE
,
149 .cm2ioctl
= LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE
,
150 .dt0ioctl
= LPDDR2_DATA0_IOCTRL_VALUE
,
151 .dt1ioctl
= LPDDR2_DATA0_IOCTRL_VALUE
,
152 .dt2ioctrl
= LPDDR2_DATA0_IOCTRL_VALUE
,
153 .dt3ioctrl
= LPDDR2_DATA0_IOCTRL_VALUE
,
154 .emif_sdram_config_ext
= 0x1,
157 const struct emif_regs emif_regs_lpddr2
= {
158 .sdram_config
= 0x808012BA,
159 .ref_ctrl
= 0x0000040D,
160 .sdram_tim1
= 0xEA86B411,
161 .sdram_tim2
= 0x103A094A,
162 .sdram_tim3
= 0x0F6BA37F,
163 .read_idle_ctrl
= 0x00050000,
164 .zq_config
= 0x50074BE4,
165 .temp_alert_config
= 0x0,
166 .emif_rd_wr_lvl_rmp_win
= 0x0,
167 .emif_rd_wr_lvl_rmp_ctl
= 0x0,
168 .emif_rd_wr_lvl_ctl
= 0x0,
169 .emif_ddr_phy_ctlr_1
= 0x0E284006,
170 .emif_rd_wr_exec_thresh
= 0x80000405,
171 .emif_ddr_ext_phy_ctrl_1
= 0x04010040,
172 .emif_ddr_ext_phy_ctrl_2
= 0x00500050,
173 .emif_ddr_ext_phy_ctrl_3
= 0x00500050,
174 .emif_ddr_ext_phy_ctrl_4
= 0x00500050,
175 .emif_ddr_ext_phy_ctrl_5
= 0x00500050,
176 .emif_prio_class_serv_map
= 0x80000001,
177 .emif_connect_id_serv_1_map
= 0x80000094,
178 .emif_connect_id_serv_2_map
= 0x00000000,
179 .emif_cos_config
= 0x000FFFFF
182 const struct ctrl_ioregs ioregs_ddr3
= {
183 .cm0ioctl
= DDR3_ADDRCTRL_IOCTRL_VALUE
,
184 .cm1ioctl
= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE
,
185 .cm2ioctl
= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE
,
186 .dt0ioctl
= DDR3_DATA0_IOCTRL_VALUE
,
187 .dt1ioctl
= DDR3_DATA0_IOCTRL_VALUE
,
188 .dt2ioctrl
= DDR3_DATA0_IOCTRL_VALUE
,
189 .dt3ioctrl
= DDR3_DATA0_IOCTRL_VALUE
,
190 .emif_sdram_config_ext
= 0xc163,
193 const struct emif_regs ddr3_emif_regs_400Mhz
= {
194 .sdram_config
= 0x638413B2,
195 .ref_ctrl
= 0x00000C30,
196 .sdram_tim1
= 0xEAAAD4DB,
197 .sdram_tim2
= 0x266B7FDA,
198 .sdram_tim3
= 0x107F8678,
199 .read_idle_ctrl
= 0x00050000,
200 .zq_config
= 0x50074BE4,
201 .temp_alert_config
= 0x0,
202 .emif_ddr_phy_ctlr_1
= 0x0E004008,
203 .emif_ddr_ext_phy_ctrl_1
= 0x08020080,
204 .emif_ddr_ext_phy_ctrl_2
= 0x00400040,
205 .emif_ddr_ext_phy_ctrl_3
= 0x00400040,
206 .emif_ddr_ext_phy_ctrl_4
= 0x00400040,
207 .emif_ddr_ext_phy_ctrl_5
= 0x00400040,
208 .emif_rd_wr_lvl_rmp_win
= 0x0,
209 .emif_rd_wr_lvl_rmp_ctl
= 0x0,
210 .emif_rd_wr_lvl_ctl
= 0x0,
211 .emif_rd_wr_exec_thresh
= 0x80000405,
212 .emif_prio_class_serv_map
= 0x80000001,
213 .emif_connect_id_serv_1_map
= 0x80000094,
214 .emif_connect_id_serv_2_map
= 0x00000000,
215 .emif_cos_config
= 0x000FFFFF
218 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
219 const struct emif_regs ddr3_emif_regs_400Mhz_beta
= {
220 .sdram_config
= 0x638413B2,
221 .ref_ctrl
= 0x00000C30,
222 .sdram_tim1
= 0xEAAAD4DB,
223 .sdram_tim2
= 0x266B7FDA,
224 .sdram_tim3
= 0x107F8678,
225 .read_idle_ctrl
= 0x00050000,
226 .zq_config
= 0x50074BE4,
227 .temp_alert_config
= 0x0,
228 .emif_ddr_phy_ctlr_1
= 0x0E004008,
229 .emif_ddr_ext_phy_ctrl_1
= 0x08020080,
230 .emif_ddr_ext_phy_ctrl_2
= 0x00000065,
231 .emif_ddr_ext_phy_ctrl_3
= 0x00000091,
232 .emif_ddr_ext_phy_ctrl_4
= 0x000000B5,
233 .emif_ddr_ext_phy_ctrl_5
= 0x000000E5,
234 .emif_rd_wr_exec_thresh
= 0x80000405,
235 .emif_prio_class_serv_map
= 0x80000001,
236 .emif_connect_id_serv_1_map
= 0x80000094,
237 .emif_connect_id_serv_2_map
= 0x00000000,
238 .emif_cos_config
= 0x000FFFFF
241 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
242 const struct emif_regs ddr3_emif_regs_400Mhz_production
= {
243 .sdram_config
= 0x638413B2,
244 .ref_ctrl
= 0x00000C30,
245 .sdram_tim1
= 0xEAAAD4DB,
246 .sdram_tim2
= 0x266B7FDA,
247 .sdram_tim3
= 0x107F8678,
248 .read_idle_ctrl
= 0x00050000,
249 .zq_config
= 0x50074BE4,
250 .temp_alert_config
= 0x0,
251 .emif_ddr_phy_ctlr_1
= 0x0E004008,
252 .emif_ddr_ext_phy_ctrl_1
= 0x08020080,
253 .emif_ddr_ext_phy_ctrl_2
= 0x00000066,
254 .emif_ddr_ext_phy_ctrl_3
= 0x00000091,
255 .emif_ddr_ext_phy_ctrl_4
= 0x000000B9,
256 .emif_ddr_ext_phy_ctrl_5
= 0x000000E6,
257 .emif_rd_wr_exec_thresh
= 0x80000405,
258 .emif_prio_class_serv_map
= 0x80000001,
259 .emif_connect_id_serv_1_map
= 0x80000094,
260 .emif_connect_id_serv_2_map
= 0x00000000,
261 .emif_cos_config
= 0x000FFFFF
264 static const struct emif_regs ddr3_sk_emif_regs_400Mhz
= {
265 .sdram_config
= 0x638413b2,
266 .sdram_config2
= 0x00000000,
267 .ref_ctrl
= 0x00000c30,
268 .sdram_tim1
= 0xeaaad4db,
269 .sdram_tim2
= 0x266b7fda,
270 .sdram_tim3
= 0x107f8678,
271 .read_idle_ctrl
= 0x00050000,
272 .zq_config
= 0x50074be4,
273 .temp_alert_config
= 0x0,
274 .emif_ddr_phy_ctlr_1
= 0x0e084008,
275 .emif_ddr_ext_phy_ctrl_1
= 0x08020080,
276 .emif_ddr_ext_phy_ctrl_2
= 0x89,
277 .emif_ddr_ext_phy_ctrl_3
= 0x90,
278 .emif_ddr_ext_phy_ctrl_4
= 0x8e,
279 .emif_ddr_ext_phy_ctrl_5
= 0x8d,
280 .emif_rd_wr_lvl_rmp_win
= 0x0,
281 .emif_rd_wr_lvl_rmp_ctl
= 0x00000000,
282 .emif_rd_wr_lvl_ctl
= 0x00000000,
283 .emif_rd_wr_exec_thresh
= 0x80000000,
284 .emif_prio_class_serv_map
= 0x80000001,
285 .emif_connect_id_serv_1_map
= 0x80000094,
286 .emif_connect_id_serv_2_map
= 0x00000000,
287 .emif_cos_config
= 0x000FFFFF
290 static const struct emif_regs ddr3_idk_emif_regs_400Mhz
= {
291 .sdram_config
= 0x61a11b32,
292 .sdram_config2
= 0x00000000,
293 .ref_ctrl
= 0x00000c30,
294 .sdram_tim1
= 0xeaaad4db,
295 .sdram_tim2
= 0x266b7fda,
296 .sdram_tim3
= 0x107f8678,
297 .read_idle_ctrl
= 0x00050000,
298 .zq_config
= 0x50074be4,
299 .temp_alert_config
= 0x00000000,
300 .emif_ddr_phy_ctlr_1
= 0x00008009,
301 .emif_ddr_ext_phy_ctrl_1
= 0x08020080,
302 .emif_ddr_ext_phy_ctrl_2
= 0x00000040,
303 .emif_ddr_ext_phy_ctrl_3
= 0x0000003e,
304 .emif_ddr_ext_phy_ctrl_4
= 0x00000051,
305 .emif_ddr_ext_phy_ctrl_5
= 0x00000051,
306 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
307 .emif_rd_wr_lvl_rmp_ctl
= 0x00000000,
308 .emif_rd_wr_lvl_ctl
= 0x00000000,
309 .emif_rd_wr_exec_thresh
= 0x00000405,
310 .emif_prio_class_serv_map
= 0x00000000,
311 .emif_connect_id_serv_1_map
= 0x00000000,
312 .emif_connect_id_serv_2_map
= 0x00000000,
313 .emif_cos_config
= 0x00ffffff
317 * get_sys_clk_index : returns the index of the sys_clk read from
318 * ctrl status register. This value is either
319 * read from efuse or sysboot pins.
321 static u32
get_sys_clk_index(void)
323 struct ctrl_stat
*ctrl
= (struct ctrl_stat
*)CTRL_BASE
;
324 u32 ind
= readl(&ctrl
->statusreg
), src
;
326 src
= (ind
& CTRL_CRYSTAL_FREQ_SRC_MASK
) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT
;
327 if (src
== CTRL_CRYSTAL_FREQ_SRC_EFUSE
) /* Value read from EFUSE */
328 return ((ind
& CTRL_CRYSTAL_FREQ_SELECTION_MASK
) >>
329 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT
);
330 else /* Value read from SYS BOOT pins */
331 return ((ind
& CTRL_SYSBOOT_15_14_MASK
) >>
332 CTRL_SYSBOOT_15_14_SHIFT
);
335 const struct dpll_params
*get_dpll_ddr_params(void)
337 int ind
= get_sys_clk_index();
339 if (board_is_eposevm())
340 return &epos_evm_dpll_ddr
[ind
];
341 else if (board_is_gpevm() || board_is_sk())
342 return &gp_evm_dpll_ddr
;
343 else if (board_is_idk())
344 return &idk_dpll_ddr
;
346 printf(" Board '%s' not supported\n", am43xx_board_name
);
353 * Returns the index for safest OPP of the device to boot.
354 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
355 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
356 * This data is read from dev_attribute register which is e-fused.
357 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
358 * OPP available. Lowest OPP starts with min_off. So returning the
359 * bit with rightmost '0'.
361 static int get_opp_offset(int max_off
, int min_off
)
363 struct ctrl_stat
*ctrl
= (struct ctrl_stat
*)CTRL_BASE
;
366 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
367 opp
= readl(&ctrl
->dev_attr
) & ~0xFFFFF000;
369 for (i
= max_off
; i
>= min_off
; i
--) {
370 offset
= opp
& (1 << i
);
378 const struct dpll_params
*get_dpll_mpu_params(void)
380 int opp
= get_opp_offset(DEV_ATTR_MAX_OFFSET
, DEV_ATTR_MIN_OFFSET
);
381 u32 ind
= get_sys_clk_index();
383 return &dpll_mpu
[ind
][opp
];
386 const struct dpll_params
*get_dpll_core_params(void)
388 int ind
= get_sys_clk_index();
390 return &dpll_core
[ind
];
393 const struct dpll_params
*get_dpll_per_params(void)
395 int ind
= get_sys_clk_index();
397 return &dpll_per
[ind
];
400 void scale_vcores_generic(u32 m
)
404 if (i2c_probe(TPS65218_CHIP_PM
))
409 mpu_vdd
= TPS65218_DCDC_VOLT_SEL_1330MV
;
412 mpu_vdd
= TPS65218_DCDC_VOLT_SEL_1260MV
;
415 mpu_vdd
= TPS65218_DCDC_VOLT_SEL_1200MV
;
418 mpu_vdd
= TPS65218_DCDC_VOLT_SEL_1100MV
;
421 mpu_vdd
= TPS65218_DCDC_VOLT_SEL_0950MV
;
424 puts("Unknown MPU clock, not scaling\n");
428 /* Set DCDC1 (CORE) voltage to 1.1V */
429 if (tps65218_voltage_update(TPS65218_DCDC1
,
430 TPS65218_DCDC_VOLT_SEL_1100MV
)) {
431 printf("%s failure\n", __func__
);
435 /* Set DCDC2 (MPU) voltage */
436 if (tps65218_voltage_update(TPS65218_DCDC2
, mpu_vdd
)) {
437 printf("%s failure\n", __func__
);
442 void scale_vcores_idk(u32 m
)
446 if (i2c_probe(TPS62362_I2C_ADDR
))
451 mpu_vdd
= TPS62362_DCDC_VOLT_SEL_1330MV
;
454 mpu_vdd
= TPS62362_DCDC_VOLT_SEL_1260MV
;
457 mpu_vdd
= TPS62362_DCDC_VOLT_SEL_1200MV
;
460 mpu_vdd
= TPS62362_DCDC_VOLT_SEL_1100MV
;
463 mpu_vdd
= TPS62362_DCDC_VOLT_SEL_1330MV
;
466 puts("Unknown MPU clock, not scaling\n");
470 /* Set VDD_MPU voltage */
471 if (tps62362_voltage_update(TPS62362_SET3
, mpu_vdd
)) {
472 printf("%s failure\n", __func__
);
477 void scale_vcores(void)
479 const struct dpll_params
*mpu_params
;
480 struct am43xx_board_id header
;
482 enable_i2c0_pin_mux();
483 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED
, CONFIG_SYS_OMAP24_I2C_SLAVE
);
484 if (read_eeprom(&header
) < 0)
485 puts("Could not get board ID.\n");
487 /* Get the frequency */
488 mpu_params
= get_dpll_mpu_params();
491 scale_vcores_idk(mpu_params
->m
);
493 scale_vcores_generic(mpu_params
->m
);
496 void set_uart_mux_conf(void)
498 enable_uart0_pin_mux();
501 void set_mux_conf_regs(void)
503 enable_board_pin_mux();
506 static void enable_vtt_regulator(void)
511 writel(GPIO_CTRL_ENABLEMODULE
, AM33XX_GPIO5_BASE
+ OMAP_GPIO_CTRL
);
513 /* enable output for GPIO5_7 */
514 writel(GPIO_SETDATAOUT(7),
515 AM33XX_GPIO5_BASE
+ OMAP_GPIO_SETDATAOUT
);
516 temp
= readl(AM33XX_GPIO5_BASE
+ OMAP_GPIO_OE
);
517 temp
= temp
& ~(GPIO_OE_ENABLE(7));
518 writel(temp
, AM33XX_GPIO5_BASE
+ OMAP_GPIO_OE
);
521 void sdram_init(void)
524 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
525 * GP EMV has 1GB DDR3 connected to EMIF
526 * along with VTT regulator.
528 if (board_is_eposevm()) {
529 config_ddr(0, &ioregs_lpddr2
, NULL
, NULL
, &emif_regs_lpddr2
, 0);
530 } else if (board_is_evm_14_or_later()) {
531 enable_vtt_regulator();
532 config_ddr(0, &ioregs_ddr3
, NULL
, NULL
,
533 &ddr3_emif_regs_400Mhz_production
, 0);
534 } else if (board_is_evm_12_or_later()) {
535 enable_vtt_regulator();
536 config_ddr(0, &ioregs_ddr3
, NULL
, NULL
,
537 &ddr3_emif_regs_400Mhz_beta
, 0);
538 } else if (board_is_gpevm()) {
539 enable_vtt_regulator();
540 config_ddr(0, &ioregs_ddr3
, NULL
, NULL
,
541 &ddr3_emif_regs_400Mhz
, 0);
542 } else if (board_is_sk()) {
543 config_ddr(400, &ioregs_ddr3
, NULL
, NULL
,
544 &ddr3_sk_emif_regs_400Mhz
, 0);
545 } else if (board_is_idk()) {
546 config_ddr(400, &ioregs_ddr3
, NULL
, NULL
,
547 &ddr3_idk_emif_regs_400Mhz
, 0);
552 /* setup board specific PMIC */
553 int power_init_board(void)
557 if (board_is_idk()) {
558 power_tps62362_init(I2C_PMIC
);
559 p
= pmic_get("TPS62362");
560 if (p
&& !pmic_probe(p
))
561 puts("PMIC: TPS62362\n");
563 power_tps65218_init(I2C_PMIC
);
564 p
= pmic_get("TPS65218_PMIC");
565 if (p
&& !pmic_probe(p
))
566 puts("PMIC: TPS65218\n");
574 struct l3f_cfg_bwlimiter
*bwlimiter
= (struct l3f_cfg_bwlimiter
*)L3F_CFG_BWLIMITER
;
575 u32 mreqprio_0
, mreqprio_1
, modena_init0_bw_fractional
,
576 modena_init0_bw_integer
, modena_init0_watermark_0
;
578 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
581 /* Clear all important bits for DSS errata that may need to be tweaked*/
582 mreqprio_0
= readl(&cdev
->mreqprio_0
) & MREQPRIO_0_SAB_INIT1_MASK
&
583 MREQPRIO_0_SAB_INIT0_MASK
;
585 mreqprio_1
= readl(&cdev
->mreqprio_1
) & MREQPRIO_1_DSS_MASK
;
587 modena_init0_bw_fractional
= readl(&bwlimiter
->modena_init0_bw_fractional
) &
588 BW_LIMITER_BW_FRAC_MASK
;
590 modena_init0_bw_integer
= readl(&bwlimiter
->modena_init0_bw_integer
) &
591 BW_LIMITER_BW_INT_MASK
;
593 modena_init0_watermark_0
= readl(&bwlimiter
->modena_init0_watermark_0
) &
594 BW_LIMITER_BW_WATERMARK_MASK
;
596 /* Setting MReq Priority of the DSS*/
600 * Set L3 Fast Configuration Register
601 * Limiting bandwith for ARM core to 700 MBPS
603 modena_init0_bw_fractional
|= 0x10;
604 modena_init0_bw_integer
|= 0x3;
606 writel(mreqprio_0
, &cdev
->mreqprio_0
);
607 writel(mreqprio_1
, &cdev
->mreqprio_1
);
609 writel(modena_init0_bw_fractional
, &bwlimiter
->modena_init0_bw_fractional
);
610 writel(modena_init0_bw_integer
, &bwlimiter
->modena_init0_bw_integer
);
611 writel(modena_init0_watermark_0
, &bwlimiter
->modena_init0_watermark_0
);
616 #ifdef CONFIG_BOARD_LATE_INIT
617 int board_late_init(void)
619 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
620 char safe_string
[HDR_NAME_LEN
+ 1];
621 struct am43xx_board_id header
;
623 if (read_eeprom(&header
) < 0)
624 puts("Could not get board ID.\n");
626 /* Now set variables based on the header. */
627 strncpy(safe_string
, (char *)header
.name
, sizeof(header
.name
));
628 safe_string
[sizeof(header
.name
)] = 0;
629 setenv("board_name", safe_string
);
631 strncpy(safe_string
, (char *)header
.version
, sizeof(header
.version
));
632 safe_string
[sizeof(header
.version
)] = 0;
633 setenv("board_rev", safe_string
);
639 #ifdef CONFIG_DRIVER_TI_CPSW
641 static void cpsw_control(int enabled
)
643 /* Additional controls can be added here */
647 static struct cpsw_slave_data cpsw_slaves
[] = {
649 .slave_reg_ofs
= 0x208,
650 .sliver_reg_ofs
= 0xd80,
654 .slave_reg_ofs
= 0x308,
655 .sliver_reg_ofs
= 0xdc0,
660 static struct cpsw_platform_data cpsw_data
= {
661 .mdio_base
= CPSW_MDIO_BASE
,
662 .cpsw_base
= CPSW_BASE
,
665 .cpdma_reg_ofs
= 0x800,
667 .slave_data
= cpsw_slaves
,
668 .ale_reg_ofs
= 0xd00,
670 .host_port_reg_ofs
= 0x108,
671 .hw_stats_reg_ofs
= 0x900,
672 .bd_ram_ofs
= 0x2000,
673 .mac_control
= (1 << 5),
674 .control
= cpsw_control
,
676 .version
= CPSW_CTRL_VERSION_2
,
679 int board_eth_init(bd_t
*bis
)
683 uint32_t mac_hi
, mac_lo
;
685 /* try reading mac address from efuse */
686 mac_lo
= readl(&cdev
->macid0l
);
687 mac_hi
= readl(&cdev
->macid0h
);
688 mac_addr
[0] = mac_hi
& 0xFF;
689 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
690 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
691 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
692 mac_addr
[4] = mac_lo
& 0xFF;
693 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
695 if (!getenv("ethaddr")) {
696 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
697 if (is_valid_ether_addr(mac_addr
))
698 eth_setenv_enetaddr("ethaddr", mac_addr
);
701 mac_lo
= readl(&cdev
->macid1l
);
702 mac_hi
= readl(&cdev
->macid1h
);
703 mac_addr
[0] = mac_hi
& 0xFF;
704 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
705 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
706 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
707 mac_addr
[4] = mac_lo
& 0xFF;
708 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
710 if (!getenv("eth1addr")) {
711 if (is_valid_ether_addr(mac_addr
))
712 eth_setenv_enetaddr("eth1addr", mac_addr
);
715 if (board_is_eposevm()) {
716 writel(RMII_MODE_ENABLE
| RMII_CHIPCKL_ENABLE
, &cdev
->miisel
);
717 cpsw_slaves
[0].phy_if
= PHY_INTERFACE_MODE_RMII
;
718 cpsw_slaves
[0].phy_addr
= 16;
719 } else if (board_is_sk()) {
720 writel(RGMII_MODE_ENABLE
, &cdev
->miisel
);
721 cpsw_slaves
[0].phy_if
= PHY_INTERFACE_MODE_RGMII
;
722 cpsw_slaves
[0].phy_addr
= 4;
723 cpsw_slaves
[1].phy_addr
= 5;
724 } else if (board_is_idk()) {
725 writel(RGMII_MODE_ENABLE
, &cdev
->miisel
);
726 cpsw_slaves
[0].phy_if
= PHY_INTERFACE_MODE_RGMII
;
727 cpsw_slaves
[0].phy_addr
= 0;
729 writel(RGMII_MODE_ENABLE
, &cdev
->miisel
);
730 cpsw_slaves
[0].phy_if
= PHY_INTERFACE_MODE_RGMII
;
731 cpsw_slaves
[0].phy_addr
= 0;
734 rv
= cpsw_register(&cpsw_data
);
736 printf("Error %d registering CPSW switch\n", rv
);