board/ti/am43xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM43XX based boards
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <i2c.h>
  13 #include <linux/errno.h>
  14 #include <spl.h>
  15 #include <usb.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/mux.h>
  20 #include <asm/arch/ddr_defs.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/emif.h>
  23 #include "../common/board_detect.h"
  24 #include "board.h"
  25 #include <power/pmic.h>
  26 #include <power/tps65218.h>
  27 #include <power/tps62362.h>
  28 #include <miiphy.h>
  29 #include <cpsw.h>
  30 #include <linux/usb/gadget.h>
  31 #include <dwc3-uboot.h>
  32 #include <dwc3-omap-uboot.h>
  33 #include <ti-usb-phy-uboot.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  38
  39 /*
  40  * Read header information from EEPROM into global structure.
  41  */
  42 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  43 void do_board_detect(void)
  44 {
  45         if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
  46                 printf("ti_i2c_eeprom_init failed\n");
  47 }
  48 #endif
  49
  50 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  51
  52 #define NUM_OPPS        6
  53
  54 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  55         {       /* 19.2 MHz */
  56                 {125, 3, 2, -1, -1, -1, -1},    /* OPP 50 */
  57                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  58                 {125, 3, 1, -1, -1, -1, -1},    /* OPP 100 */
  59                 {150, 3, 1, -1, -1, -1, -1},    /* OPP 120 */
  60                 {125, 2, 1, -1, -1, -1, -1},    /* OPP TB */
  61                 {625, 11, 1, -1, -1, -1, -1}    /* OPP NT */
  62         },
  63         {       /* 24 MHz */
  64                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  65                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  66                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  67                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  68                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  69                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  70         },
  71         {       /* 25 MHz */
  72                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
  73                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  74                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
  75                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
  76                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
  77                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
  78         },
  79         {       /* 26 MHz */
  80                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
  81                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  82                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
  83                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
  84                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
  85                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
  86         },
  87 };
  88
  89 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  90                 {625, 11, -1, -1, 10, 8, 4},    /* 19.2 MHz */
  91                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
  92                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
  93                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
  94 };
  95
  96 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
  97                 {400, 7, 5, -1, -1, -1, -1},    /* 19.2 MHz */
  98                 {400, 9, 5, -1, -1, -1, -1},    /* 24 MHz */
  99                 {384, 9, 5, -1, -1, -1, -1},    /* 25 MHz */
 100                 {480, 12, 5, -1, -1, -1, -1}    /* 26 MHz */
 101 };
 102
 103 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
 104                 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
 105                 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
 106                 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
 107                 {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
 108 };
 109
 110 const struct dpll_params gp_evm_dpll_ddr = {
 111                 50, 2, 1, -1, 2, -1, -1};
 112
 113 static const struct dpll_params idk_dpll_ddr = {
 114         400, 23, 1, -1, 2, -1, -1
 115 };
 116
 117 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 118         0x00500050,
 119         0x00350035,
 120         0x00350035,
 121         0x00350035,
 122         0x00350035,
 123         0x00350035,
 124         0x00000000,
 125         0x00000000,
 126         0x00000000,
 127         0x00000000,
 128         0x00000000,
 129         0x00000000,
 130         0x00000000,
 131         0x00000000,
 132         0x00000000,
 133         0x00000000,
 134         0x00000000,
 135         0x00000000,
 136         0x40001000,
 137         0x08102040
 138 };
 139
 140 const struct ctrl_ioregs ioregs_lpddr2 = {
 141         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 142         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 143         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 144         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 145         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 146         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 147         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 148         .emif_sdram_config_ext  = 0x1,
 149 };
 150
 151 const struct emif_regs emif_regs_lpddr2 = {
 152         .sdram_config                   = 0x808012BA,
 153         .ref_ctrl                       = 0x0000040D,
 154         .sdram_tim1                     = 0xEA86B411,
 155         .sdram_tim2                     = 0x103A094A,
 156         .sdram_tim3                     = 0x0F6BA37F,
 157         .read_idle_ctrl                 = 0x00050000,
 158         .zq_config                      = 0x50074BE4,
 159         .temp_alert_config              = 0x0,
 160         .emif_rd_wr_lvl_rmp_win         = 0x0,
 161         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 162         .emif_rd_wr_lvl_ctl             = 0x0,
 163         .emif_ddr_phy_ctlr_1            = 0x0E284006,
 164         .emif_rd_wr_exec_thresh         = 0x80000405,
 165         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 166         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 167         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 168         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 169         .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
 170         .emif_prio_class_serv_map       = 0x80000001,
 171         .emif_connect_id_serv_1_map     = 0x80000094,
 172         .emif_connect_id_serv_2_map     = 0x00000000,
 173         .emif_cos_config                        = 0x000FFFFF
 174 };
 175
 176 const struct ctrl_ioregs ioregs_ddr3 = {
 177         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 178         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 179         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 180         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 181         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 182         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 183         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 184         .emif_sdram_config_ext  = 0xc163,
 185 };
 186
 187 const struct emif_regs ddr3_emif_regs_400Mhz = {
 188         .sdram_config                   = 0x638413B2,
 189         .ref_ctrl                       = 0x00000C30,
 190         .sdram_tim1                     = 0xEAAAD4DB,
 191         .sdram_tim2                     = 0x266B7FDA,
 192         .sdram_tim3                     = 0x107F8678,
 193         .read_idle_ctrl                 = 0x00050000,
 194         .zq_config                      = 0x50074BE4,
 195         .temp_alert_config              = 0x0,
 196         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 197         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 198         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 199         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 200         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 201         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 202         .emif_rd_wr_lvl_rmp_win         = 0x0,
 203         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 204         .emif_rd_wr_lvl_ctl             = 0x0,
 205         .emif_rd_wr_exec_thresh         = 0x80000405,
 206         .emif_prio_class_serv_map       = 0x80000001,
 207         .emif_connect_id_serv_1_map     = 0x80000094,
 208         .emif_connect_id_serv_2_map     = 0x00000000,
 209         .emif_cos_config                = 0x000FFFFF
 210 };
 211
 212 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 213 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 214         .sdram_config                   = 0x638413B2,
 215         .ref_ctrl                       = 0x00000C30,
 216         .sdram_tim1                     = 0xEAAAD4DB,
 217         .sdram_tim2                     = 0x266B7FDA,
 218         .sdram_tim3                     = 0x107F8678,
 219         .read_idle_ctrl                 = 0x00050000,
 220         .zq_config                      = 0x50074BE4,
 221         .temp_alert_config              = 0x0,
 222         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 223         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 224         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 225         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 226         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 227         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 228         .emif_rd_wr_exec_thresh         = 0x80000405,
 229         .emif_prio_class_serv_map       = 0x80000001,
 230         .emif_connect_id_serv_1_map     = 0x80000094,
 231         .emif_connect_id_serv_2_map     = 0x00000000,
 232         .emif_cos_config                = 0x000FFFFF
 233 };
 234
 235 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 236 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 237         .sdram_config                   = 0x638413B2,
 238         .ref_ctrl                       = 0x00000C30,
 239         .sdram_tim1                     = 0xEAAAD4DB,
 240         .sdram_tim2                     = 0x266B7FDA,
 241         .sdram_tim3                     = 0x107F8678,
 242         .read_idle_ctrl                 = 0x00050000,
 243         .zq_config                      = 0x50074BE4,
 244         .temp_alert_config              = 0x0,
 245         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 246         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 247         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 248         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 249         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 250         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 251         .emif_rd_wr_exec_thresh         = 0x80000405,
 252         .emif_prio_class_serv_map       = 0x80000001,
 253         .emif_connect_id_serv_1_map     = 0x80000094,
 254         .emif_connect_id_serv_2_map     = 0x00000000,
 255         .emif_cos_config                = 0x000FFFFF
 256 };
 257
 258 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 259         .sdram_config                   = 0x638413b2,
 260         .sdram_config2                  = 0x00000000,
 261         .ref_ctrl                       = 0x00000c30,
 262         .sdram_tim1                     = 0xeaaad4db,
 263         .sdram_tim2                     = 0x266b7fda,
 264         .sdram_tim3                     = 0x107f8678,
 265         .read_idle_ctrl                 = 0x00050000,
 266         .zq_config                      = 0x50074be4,
 267         .temp_alert_config              = 0x0,
 268         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 269         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 270         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 271         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 272         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 273         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 274         .emif_rd_wr_lvl_rmp_win         = 0x0,
 275         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 276         .emif_rd_wr_lvl_ctl             = 0x00000000,
 277         .emif_rd_wr_exec_thresh         = 0x80000000,
 278         .emif_prio_class_serv_map       = 0x80000001,
 279         .emif_connect_id_serv_1_map     = 0x80000094,
 280         .emif_connect_id_serv_2_map     = 0x00000000,
 281         .emif_cos_config                = 0x000FFFFF
 282 };
 283
 284 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
 285         .sdram_config                   = 0x61a11b32,
 286         .sdram_config2                  = 0x00000000,
 287         .ref_ctrl                       = 0x00000c30,
 288         .sdram_tim1                     = 0xeaaad4db,
 289         .sdram_tim2                     = 0x266b7fda,
 290         .sdram_tim3                     = 0x107f8678,
 291         .read_idle_ctrl                 = 0x00050000,
 292         .zq_config                      = 0x50074be4,
 293         .temp_alert_config              = 0x00000000,
 294         .emif_ddr_phy_ctlr_1            = 0x00008009,
 295         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 296         .emif_ddr_ext_phy_ctrl_2        = 0x00000040,
 297         .emif_ddr_ext_phy_ctrl_3        = 0x0000003e,
 298         .emif_ddr_ext_phy_ctrl_4        = 0x00000051,
 299         .emif_ddr_ext_phy_ctrl_5        = 0x00000051,
 300         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 301         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 302         .emif_rd_wr_lvl_ctl             = 0x00000000,
 303         .emif_rd_wr_exec_thresh         = 0x00000405,
 304         .emif_prio_class_serv_map       = 0x00000000,
 305         .emif_connect_id_serv_1_map     = 0x00000000,
 306         .emif_connect_id_serv_2_map     = 0x00000000,
 307         .emif_cos_config                = 0x00ffffff
 308 };
 309
 310 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 311 {
 312         if (board_is_eposevm()) {
 313                 *regs = ext_phy_ctrl_const_base_lpddr2;
 314                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 315         }
 316
 317         return;
 318 }
 319
 320 /*
 321  * get_sys_clk_index : returns the index of the sys_clk read from
 322  *                      ctrl status register. This value is either
 323  *                      read from efuse or sysboot pins.
 324  */
 325 static u32 get_sys_clk_index(void)
 326 {
 327         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 328         u32 ind = readl(&ctrl->statusreg), src;
 329
 330         src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
 331         if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
 332                 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
 333                         CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
 334         else /* Value read from SYS BOOT pins */
 335                 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
 336                         CTRL_SYSBOOT_15_14_SHIFT);
 337 }
 338
 339 const struct dpll_params *get_dpll_ddr_params(void)
 340 {
 341         int ind = get_sys_clk_index();
 342
 343         if (board_is_eposevm())
 344                 return &epos_evm_dpll_ddr[ind];
 345         else if (board_is_evm() || board_is_sk())
 346                 return &gp_evm_dpll_ddr;
 347         else if (board_is_idk())
 348                 return &idk_dpll_ddr;
 349
 350         printf(" Board '%s' not supported\n", board_ti_get_name());
 351         return NULL;
 352 }
 353
 354
 355 /*
 356  * get_opp_offset:
 357  * Returns the index for safest OPP of the device to boot.
 358  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 359  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 360  * This data is read from dev_attribute register which is e-fused.
 361  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 362  * OPP available. Lowest OPP starts with min_off. So returning the
 363  * bit with rightmost '0'.
 364  */
 365 static int get_opp_offset(int max_off, int min_off)
 366 {
 367         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 368         int opp, offset, i;
 369
 370         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 371         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 372
 373         for (i = max_off; i >= min_off; i--) {
 374                 offset = opp & (1 << i);
 375                 if (!offset)
 376                         return i;
 377         }
 378
 379         return min_off;
 380 }
 381
 382 const struct dpll_params *get_dpll_mpu_params(void)
 383 {
 384         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 385         u32 ind = get_sys_clk_index();
 386
 387         return &dpll_mpu[ind][opp];
 388 }
 389
 390 const struct dpll_params *get_dpll_core_params(void)
 391 {
 392         int ind = get_sys_clk_index();
 393
 394         return &dpll_core[ind];
 395 }
 396
 397 const struct dpll_params *get_dpll_per_params(void)
 398 {
 399         int ind = get_sys_clk_index();
 400
 401         return &dpll_per[ind];
 402 }
 403
 404 void scale_vcores_generic(u32 m)
 405 {
 406         int mpu_vdd;
 407
 408         if (i2c_probe(TPS65218_CHIP_PM))
 409                 return;
 410
 411         switch (m) {
 412         case 1000:
 413                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 414                 break;
 415         case 800:
 416                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
 417                 break;
 418         case 720:
 419                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
 420                 break;
 421         case 600:
 422                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 423                 break;
 424         case 300:
 425                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
 426                 break;
 427         default:
 428                 puts("Unknown MPU clock, not scaling\n");
 429                 return;
 430         }
 431
 432         /* Set DCDC1 (CORE) voltage to 1.1V */
 433         if (tps65218_voltage_update(TPS65218_DCDC1,
 434                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 435                 printf("%s failure\n", __func__);
 436                 return;
 437         }
 438
 439         /* Set DCDC2 (MPU) voltage */
 440         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 441                 printf("%s failure\n", __func__);
 442                 return;
 443         }
 444 }
 445
 446 void scale_vcores_idk(u32 m)
 447 {
 448         int mpu_vdd;
 449
 450         if (i2c_probe(TPS62362_I2C_ADDR))
 451                 return;
 452
 453         switch (m) {
 454         case 1000:
 455                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 456                 break;
 457         case 800:
 458                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
 459                 break;
 460         case 720:
 461                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
 462                 break;
 463         case 600:
 464                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
 465                 break;
 466         case 300:
 467                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 468                 break;
 469         default:
 470                 puts("Unknown MPU clock, not scaling\n");
 471                 return;
 472         }
 473
 474         /* Set VDD_MPU voltage */
 475         if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
 476                 printf("%s failure\n", __func__);
 477                 return;
 478         }
 479 }
 480
 481 void gpi2c_init(void)
 482 {
 483         /* When needed to be invoked prior to BSS initialization */
 484         static bool first_time = true;
 485
 486         if (first_time) {
 487                 enable_i2c0_pin_mux();
 488                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 489                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 490                 first_time = false;
 491         }
 492 }
 493
 494 void scale_vcores(void)
 495 {
 496         const struct dpll_params *mpu_params;
 497
 498         /* Ensure I2C is initialized for PMIC configuration */
 499         gpi2c_init();
 500
 501         /* Get the frequency */
 502         mpu_params = get_dpll_mpu_params();
 503
 504         if (board_is_idk())
 505                 scale_vcores_idk(mpu_params->m);
 506         else
 507                 scale_vcores_generic(mpu_params->m);
 508 }
 509
 510 void set_uart_mux_conf(void)
 511 {
 512         enable_uart0_pin_mux();
 513 }
 514
 515 void set_mux_conf_regs(void)
 516 {
 517         enable_board_pin_mux();
 518 }
 519
 520 static void enable_vtt_regulator(void)
 521 {
 522         u32 temp;
 523
 524         /* enable module */
 525         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 526
 527         /* enable output for GPIO5_7 */
 528         writel(GPIO_SETDATAOUT(7),
 529                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 530         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 531         temp = temp & ~(GPIO_OE_ENABLE(7));
 532         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 533 }
 534
 535 void sdram_init(void)
 536 {
 537         /*
 538          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 539          * GP EMV has 1GB DDR3 connected to EMIF
 540          * along with VTT regulator.
 541          */
 542         if (board_is_eposevm()) {
 543                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 544         } else if (board_is_evm_14_or_later()) {
 545                 enable_vtt_regulator();
 546                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 547                            &ddr3_emif_regs_400Mhz_production, 0);
 548         } else if (board_is_evm_12_or_later()) {
 549                 enable_vtt_regulator();
 550                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 551                            &ddr3_emif_regs_400Mhz_beta, 0);
 552         } else if (board_is_evm()) {
 553                 enable_vtt_regulator();
 554                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 555                            &ddr3_emif_regs_400Mhz, 0);
 556         } else if (board_is_sk()) {
 557                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 558                            &ddr3_sk_emif_regs_400Mhz, 0);
 559         } else if (board_is_idk()) {
 560                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 561                            &ddr3_idk_emif_regs_400Mhz, 0);
 562         }
 563 }
 564 #endif
 565
 566 /* setup board specific PMIC */
 567 int power_init_board(void)
 568 {
 569         struct pmic *p;
 570
 571         if (board_is_idk()) {
 572                 power_tps62362_init(I2C_PMIC);
 573                 p = pmic_get("TPS62362");
 574                 if (p && !pmic_probe(p))
 575                         puts("PMIC:  TPS62362\n");
 576         } else {
 577                 power_tps65218_init(I2C_PMIC);
 578                 p = pmic_get("TPS65218_PMIC");
 579                 if (p && !pmic_probe(p))
 580                         puts("PMIC:  TPS65218\n");
 581         }
 582
 583         return 0;
 584 }
 585
 586 int board_init(void)
 587 {
 588         struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 589         u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 590             modena_init0_bw_integer, modena_init0_watermark_0;
 591
 592         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 593         gpmc_init();
 594
 595         /* Clear all important bits for DSS errata that may need to be tweaked*/
 596         mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 597                            MREQPRIO_0_SAB_INIT0_MASK;
 598
 599         mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 600
 601         modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 602                                            BW_LIMITER_BW_FRAC_MASK;
 603
 604         modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 605                                         BW_LIMITER_BW_INT_MASK;
 606
 607         modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 608                                          BW_LIMITER_BW_WATERMARK_MASK;
 609
 610         /* Setting MReq Priority of the DSS*/
 611         mreqprio_0 |= 0x77;
 612
 613         /*
 614          * Set L3 Fast Configuration Register
 615          * Limiting bandwith for ARM core to 700 MBPS
 616          */
 617         modena_init0_bw_fractional |= 0x10;
 618         modena_init0_bw_integer |= 0x3;
 619
 620         writel(mreqprio_0, &cdev->mreqprio_0);
 621         writel(mreqprio_1, &cdev->mreqprio_1);
 622
 623         writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 624         writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 625         writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 626
 627         return 0;
 628 }
 629
 630 #ifdef CONFIG_BOARD_LATE_INIT
 631 int board_late_init(void)
 632 {
 633 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 634         set_board_info_env(NULL);
 635
 636         /*
 637          * Default FIT boot on HS devices. Non FIT images are not allowed
 638          * on HS devices.
 639          */
 640         if (get_device_type() == HS_DEVICE)
 641                 setenv("boot_fit", "1");
 642 #endif
 643         return 0;
 644 }
 645 #endif
 646
 647 #ifdef CONFIG_USB_DWC3
 648 static struct dwc3_device usb_otg_ss1 = {
 649         .maximum_speed = USB_SPEED_HIGH,
 650         .base = USB_OTG_SS1_BASE,
 651         .tx_fifo_resize = false,
 652         .index = 0,
 653 };
 654
 655 static struct dwc3_omap_device usb_otg_ss1_glue = {
 656         .base = (void *)USB_OTG_SS1_GLUE_BASE,
 657         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 658         .index = 0,
 659 };
 660
 661 static struct ti_usb_phy_device usb_phy1_device = {
 662         .usb2_phy_power = (void *)USB2_PHY1_POWER,
 663         .index = 0,
 664 };
 665
 666 static struct dwc3_device usb_otg_ss2 = {
 667         .maximum_speed = USB_SPEED_HIGH,
 668         .base = USB_OTG_SS2_BASE,
 669         .tx_fifo_resize = false,
 670         .index = 1,
 671 };
 672
 673 static struct dwc3_omap_device usb_otg_ss2_glue = {
 674         .base = (void *)USB_OTG_SS2_GLUE_BASE,
 675         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 676         .index = 1,
 677 };
 678
 679 static struct ti_usb_phy_device usb_phy2_device = {
 680         .usb2_phy_power = (void *)USB2_PHY2_POWER,
 681         .index = 1,
 682 };
 683
 684 int usb_gadget_handle_interrupts(int index)
 685 {
 686         u32 status;
 687
 688         status = dwc3_omap_uboot_interrupt_status(index);
 689         if (status)
 690                 dwc3_uboot_handle_interrupt(index);
 691
 692         return 0;
 693 }
 694 #endif /* CONFIG_USB_DWC3 */
 695
 696 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 697 int board_usb_init(int index, enum usb_init_type init)
 698 {
 699         enable_usb_clocks(index);
 700 #ifdef CONFIG_USB_DWC3
 701         switch (index) {
 702         case 0:
 703                 if (init == USB_INIT_DEVICE) {
 704                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 705                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 706                         dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 707                         ti_usb_phy_uboot_init(&usb_phy1_device);
 708                         dwc3_uboot_init(&usb_otg_ss1);
 709                 }
 710                 break;
 711         case 1:
 712                 if (init == USB_INIT_DEVICE) {
 713                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 714                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 715                         ti_usb_phy_uboot_init(&usb_phy2_device);
 716                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 717                         dwc3_uboot_init(&usb_otg_ss2);
 718                 }
 719                 break;
 720         default:
 721                 printf("Invalid Controller Index\n");
 722         }
 723 #endif
 724
 725         return 0;
 726 }
 727
 728 int board_usb_cleanup(int index, enum usb_init_type init)
 729 {
 730 #ifdef CONFIG_USB_DWC3
 731         switch (index) {
 732         case 0:
 733         case 1:
 734                 if (init == USB_INIT_DEVICE) {
 735                         ti_usb_phy_uboot_exit(index);
 736                         dwc3_uboot_exit(index);
 737                         dwc3_omap_uboot_exit(index);
 738                 }
 739                 break;
 740         default:
 741                 printf("Invalid Controller Index\n");
 742         }
 743 #endif
 744         disable_usb_clocks(index);
 745
 746         return 0;
 747 }
 748 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 749
 750 #ifdef CONFIG_DRIVER_TI_CPSW
 751
 752 static void cpsw_control(int enabled)
 753 {
 754         /* Additional controls can be added here */
 755         return;
 756 }
 757
 758 static struct cpsw_slave_data cpsw_slaves[] = {
 759         {
 760                 .slave_reg_ofs  = 0x208,
 761                 .sliver_reg_ofs = 0xd80,
 762                 .phy_addr       = 16,
 763         },
 764         {
 765                 .slave_reg_ofs  = 0x308,
 766                 .sliver_reg_ofs = 0xdc0,
 767                 .phy_addr       = 1,
 768         },
 769 };
 770
 771 static struct cpsw_platform_data cpsw_data = {
 772         .mdio_base              = CPSW_MDIO_BASE,
 773         .cpsw_base              = CPSW_BASE,
 774         .mdio_div               = 0xff,
 775         .channels               = 8,
 776         .cpdma_reg_ofs          = 0x800,
 777         .slaves                 = 1,
 778         .slave_data             = cpsw_slaves,
 779         .ale_reg_ofs            = 0xd00,
 780         .ale_entries            = 1024,
 781         .host_port_reg_ofs      = 0x108,
 782         .hw_stats_reg_ofs       = 0x900,
 783         .bd_ram_ofs             = 0x2000,
 784         .mac_control            = (1 << 5),
 785         .control                = cpsw_control,
 786         .host_port_num          = 0,
 787         .version                = CPSW_CTRL_VERSION_2,
 788 };
 789
 790 int board_eth_init(bd_t *bis)
 791 {
 792         int rv;
 793         uint8_t mac_addr[6];
 794         uint32_t mac_hi, mac_lo;
 795
 796         /* try reading mac address from efuse */
 797         mac_lo = readl(&cdev->macid0l);
 798         mac_hi = readl(&cdev->macid0h);
 799         mac_addr[0] = mac_hi & 0xFF;
 800         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 801         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 802         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 803         mac_addr[4] = mac_lo & 0xFF;
 804         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 805
 806         if (!getenv("ethaddr")) {
 807                 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
 808                 if (is_valid_ethaddr(mac_addr))
 809                         eth_setenv_enetaddr("ethaddr", mac_addr);
 810         }
 811
 812         mac_lo = readl(&cdev->macid1l);
 813         mac_hi = readl(&cdev->macid1h);
 814         mac_addr[0] = mac_hi & 0xFF;
 815         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 816         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 817         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 818         mac_addr[4] = mac_lo & 0xFF;
 819         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 820
 821         if (!getenv("eth1addr")) {
 822                 if (is_valid_ethaddr(mac_addr))
 823                         eth_setenv_enetaddr("eth1addr", mac_addr);
 824         }
 825
 826         if (board_is_eposevm()) {
 827                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 828                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 829                 cpsw_slaves[0].phy_addr = 16;
 830         } else if (board_is_sk()) {
 831                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 832                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 833                 cpsw_slaves[0].phy_addr = 4;
 834                 cpsw_slaves[1].phy_addr = 5;
 835         } else if (board_is_idk()) {
 836                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 837                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 838                 cpsw_slaves[0].phy_addr = 0;
 839         } else {
 840                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 841                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 842                 cpsw_slaves[0].phy_addr = 0;
 843         }
 844
 845         rv = cpsw_register(&cpsw_data);
 846         if (rv < 0)
 847                 printf("Error %d registering CPSW switch\n", rv);
 848
 849         return rv;
 850 }
 851 #endif
 852
 853 #ifdef CONFIG_SPL_LOAD_FIT
 854 int board_fit_config_name_match(const char *name)
 855 {
 856         if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
 857                 return 0;
 858         else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
 859                 return 0;
 860         else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
 861                 return 0;
 862         else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
 863                 return 0;
 864         else
 865                 return -1;
 866 }
 867 #endif
 868
 869 #ifdef CONFIG_TI_SECURE_DEVICE
 870 void board_fit_image_post_process(void **p_image, size_t *p_size)
 871 {
 872         secure_boot_verify_image(p_image, p_size);
 873 }
 874 #endif