4 * Board functions for TI AM43XX based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/errno.h>
16 #include <asm/omap_sec_common.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/mux.h>
20 #include <asm/arch/ddr_defs.h>
21 #include <asm/arch/gpio.h>
23 #include "../common/board_detect.h"
25 #include <power/pmic.h>
26 #include <power/tps65218.h>
27 #include <power/tps62362.h>
30 #include <linux/usb/gadget.h>
31 #include <dwc3-uboot.h>
32 #include <dwc3-omap-uboot.h>
33 #include <ti-usb-phy-uboot.h>
35 DECLARE_GLOBAL_DATA_PTR
;
37 static struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
40 * Read header information from EEPROM into global structure.
42 #ifdef CONFIG_TI_I2C_BOARD_DETECT
43 void do_board_detect(void)
45 if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR
))
46 printf("ti_i2c_eeprom_init failed\n");
50 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
52 const struct dpll_params dpll_mpu
[NUM_CRYSTAL_FREQ
][NUM_OPPS
] = {
54 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
55 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
56 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
57 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
58 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
59 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
62 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
63 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
64 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
65 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
66 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
67 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
70 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
71 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
72 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
73 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
74 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
75 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
78 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
79 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
80 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
81 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
82 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
83 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
87 const struct dpll_params dpll_core
[NUM_CRYSTAL_FREQ
] = {
88 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
89 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
90 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
91 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
94 const struct dpll_params dpll_per
[NUM_CRYSTAL_FREQ
] = {
95 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
96 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
97 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
98 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
101 const struct dpll_params epos_evm_dpll_ddr
[NUM_CRYSTAL_FREQ
] = {
102 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
103 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
104 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
105 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
108 const struct dpll_params gp_evm_dpll_ddr
= {
109 50, 2, 1, -1, 2, -1, -1};
111 static const struct dpll_params idk_dpll_ddr
= {
112 400, 23, 1, -1, 2, -1, -1
115 static const u32 ext_phy_ctrl_const_base_lpddr2
[] = {
138 const struct ctrl_ioregs ioregs_lpddr2
= {
139 .cm0ioctl
= LPDDR2_ADDRCTRL_IOCTRL_VALUE
,
140 .cm1ioctl
= LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE
,
141 .cm2ioctl
= LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE
,
142 .dt0ioctl
= LPDDR2_DATA0_IOCTRL_VALUE
,
143 .dt1ioctl
= LPDDR2_DATA0_IOCTRL_VALUE
,
144 .dt2ioctrl
= LPDDR2_DATA0_IOCTRL_VALUE
,
145 .dt3ioctrl
= LPDDR2_DATA0_IOCTRL_VALUE
,
146 .emif_sdram_config_ext
= 0x1,
149 const struct emif_regs emif_regs_lpddr2
= {
150 .sdram_config
= 0x808012BA,
151 .ref_ctrl
= 0x0000040D,
152 .sdram_tim1
= 0xEA86B411,
153 .sdram_tim2
= 0x103A094A,
154 .sdram_tim3
= 0x0F6BA37F,
155 .read_idle_ctrl
= 0x00050000,
156 .zq_config
= 0x50074BE4,
157 .temp_alert_config
= 0x0,
158 .emif_rd_wr_lvl_rmp_win
= 0x0,
159 .emif_rd_wr_lvl_rmp_ctl
= 0x0,
160 .emif_rd_wr_lvl_ctl
= 0x0,
161 .emif_ddr_phy_ctlr_1
= 0x0E284006,
162 .emif_rd_wr_exec_thresh
= 0x80000405,
163 .emif_ddr_ext_phy_ctrl_1
= 0x04010040,
164 .emif_ddr_ext_phy_ctrl_2
= 0x00500050,
165 .emif_ddr_ext_phy_ctrl_3
= 0x00500050,
166 .emif_ddr_ext_phy_ctrl_4
= 0x00500050,
167 .emif_ddr_ext_phy_ctrl_5
= 0x00500050,
168 .emif_prio_class_serv_map
= 0x80000001,
169 .emif_connect_id_serv_1_map
= 0x80000094,
170 .emif_connect_id_serv_2_map
= 0x00000000,
171 .emif_cos_config
= 0x000FFFFF
174 const struct ctrl_ioregs ioregs_ddr3
= {
175 .cm0ioctl
= DDR3_ADDRCTRL_IOCTRL_VALUE
,
176 .cm1ioctl
= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE
,
177 .cm2ioctl
= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE
,
178 .dt0ioctl
= DDR3_DATA0_IOCTRL_VALUE
,
179 .dt1ioctl
= DDR3_DATA0_IOCTRL_VALUE
,
180 .dt2ioctrl
= DDR3_DATA0_IOCTRL_VALUE
,
181 .dt3ioctrl
= DDR3_DATA0_IOCTRL_VALUE
,
182 .emif_sdram_config_ext
= 0xc163,
185 const struct emif_regs ddr3_emif_regs_400Mhz
= {
186 .sdram_config
= 0x638413B2,
187 .ref_ctrl
= 0x00000C30,
188 .sdram_tim1
= 0xEAAAD4DB,
189 .sdram_tim2
= 0x266B7FDA,
190 .sdram_tim3
= 0x107F8678,
191 .read_idle_ctrl
= 0x00050000,
192 .zq_config
= 0x50074BE4,
193 .temp_alert_config
= 0x0,
194 .emif_ddr_phy_ctlr_1
= 0x0E004008,
195 .emif_ddr_ext_phy_ctrl_1
= 0x08020080,
196 .emif_ddr_ext_phy_ctrl_2
= 0x00400040,
197 .emif_ddr_ext_phy_ctrl_3
= 0x00400040,
198 .emif_ddr_ext_phy_ctrl_4
= 0x00400040,
199 .emif_ddr_ext_phy_ctrl_5
= 0x00400040,
200 .emif_rd_wr_lvl_rmp_win
= 0x0,
201 .emif_rd_wr_lvl_rmp_ctl
= 0x0,
202 .emif_rd_wr_lvl_ctl
= 0x0,
203 .emif_rd_wr_exec_thresh
= 0x80000405,
204 .emif_prio_class_serv_map
= 0x80000001,
205 .emif_connect_id_serv_1_map
= 0x80000094,
206 .emif_connect_id_serv_2_map
= 0x00000000,
207 .emif_cos_config
= 0x000FFFFF
210 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
211 const struct emif_regs ddr3_emif_regs_400Mhz_beta
= {
212 .sdram_config
= 0x638413B2,
213 .ref_ctrl
= 0x00000C30,
214 .sdram_tim1
= 0xEAAAD4DB,
215 .sdram_tim2
= 0x266B7FDA,
216 .sdram_tim3
= 0x107F8678,
217 .read_idle_ctrl
= 0x00050000,
218 .zq_config
= 0x50074BE4,
219 .temp_alert_config
= 0x0,
220 .emif_ddr_phy_ctlr_1
= 0x0E004008,
221 .emif_ddr_ext_phy_ctrl_1
= 0x08020080,
222 .emif_ddr_ext_phy_ctrl_2
= 0x00000065,
223 .emif_ddr_ext_phy_ctrl_3
= 0x00000091,
224 .emif_ddr_ext_phy_ctrl_4
= 0x000000B5,
225 .emif_ddr_ext_phy_ctrl_5
= 0x000000E5,
226 .emif_rd_wr_exec_thresh
= 0x80000405,
227 .emif_prio_class_serv_map
= 0x80000001,
228 .emif_connect_id_serv_1_map
= 0x80000094,
229 .emif_connect_id_serv_2_map
= 0x00000000,
230 .emif_cos_config
= 0x000FFFFF
233 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
234 const struct emif_regs ddr3_emif_regs_400Mhz_production
= {
235 .sdram_config
= 0x638413B2,
236 .ref_ctrl
= 0x00000C30,
237 .sdram_tim1
= 0xEAAAD4DB,
238 .sdram_tim2
= 0x266B7FDA,
239 .sdram_tim3
= 0x107F8678,
240 .read_idle_ctrl
= 0x00050000,
241 .zq_config
= 0x50074BE4,
242 .temp_alert_config
= 0x0,
243 .emif_ddr_phy_ctlr_1
= 0x0E004008,
244 .emif_ddr_ext_phy_ctrl_1
= 0x08020080,
245 .emif_ddr_ext_phy_ctrl_2
= 0x00000066,
246 .emif_ddr_ext_phy_ctrl_3
= 0x00000091,
247 .emif_ddr_ext_phy_ctrl_4
= 0x000000B9,
248 .emif_ddr_ext_phy_ctrl_5
= 0x000000E6,
249 .emif_rd_wr_exec_thresh
= 0x80000405,
250 .emif_prio_class_serv_map
= 0x80000001,
251 .emif_connect_id_serv_1_map
= 0x80000094,
252 .emif_connect_id_serv_2_map
= 0x00000000,
253 .emif_cos_config
= 0x000FFFFF
256 static const struct emif_regs ddr3_sk_emif_regs_400Mhz
= {
257 .sdram_config
= 0x638413b2,
258 .sdram_config2
= 0x00000000,
259 .ref_ctrl
= 0x00000c30,
260 .sdram_tim1
= 0xeaaad4db,
261 .sdram_tim2
= 0x266b7fda,
262 .sdram_tim3
= 0x107f8678,
263 .read_idle_ctrl
= 0x00050000,
264 .zq_config
= 0x50074be4,
265 .temp_alert_config
= 0x0,
266 .emif_ddr_phy_ctlr_1
= 0x0e084008,
267 .emif_ddr_ext_phy_ctrl_1
= 0x08020080,
268 .emif_ddr_ext_phy_ctrl_2
= 0x89,
269 .emif_ddr_ext_phy_ctrl_3
= 0x90,
270 .emif_ddr_ext_phy_ctrl_4
= 0x8e,
271 .emif_ddr_ext_phy_ctrl_5
= 0x8d,
272 .emif_rd_wr_lvl_rmp_win
= 0x0,
273 .emif_rd_wr_lvl_rmp_ctl
= 0x00000000,
274 .emif_rd_wr_lvl_ctl
= 0x00000000,
275 .emif_rd_wr_exec_thresh
= 0x80000000,
276 .emif_prio_class_serv_map
= 0x80000001,
277 .emif_connect_id_serv_1_map
= 0x80000094,
278 .emif_connect_id_serv_2_map
= 0x00000000,
279 .emif_cos_config
= 0x000FFFFF
282 static const struct emif_regs ddr3_idk_emif_regs_400Mhz
= {
283 .sdram_config
= 0x61a11b32,
284 .sdram_config2
= 0x00000000,
285 .ref_ctrl
= 0x00000c30,
286 .sdram_tim1
= 0xeaaad4db,
287 .sdram_tim2
= 0x266b7fda,
288 .sdram_tim3
= 0x107f8678,
289 .read_idle_ctrl
= 0x00050000,
290 .zq_config
= 0x50074be4,
291 .temp_alert_config
= 0x00000000,
292 .emif_ddr_phy_ctlr_1
= 0x00008009,
293 .emif_ddr_ext_phy_ctrl_1
= 0x08020080,
294 .emif_ddr_ext_phy_ctrl_2
= 0x00000040,
295 .emif_ddr_ext_phy_ctrl_3
= 0x0000003e,
296 .emif_ddr_ext_phy_ctrl_4
= 0x00000051,
297 .emif_ddr_ext_phy_ctrl_5
= 0x00000051,
298 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
299 .emif_rd_wr_lvl_rmp_ctl
= 0x00000000,
300 .emif_rd_wr_lvl_ctl
= 0x00000000,
301 .emif_rd_wr_exec_thresh
= 0x00000405,
302 .emif_prio_class_serv_map
= 0x00000000,
303 .emif_connect_id_serv_1_map
= 0x00000000,
304 .emif_connect_id_serv_2_map
= 0x00000000,
305 .emif_cos_config
= 0x00ffffff
308 void emif_get_ext_phy_ctrl_const_regs(const u32
**regs
, u32
*size
)
310 if (board_is_eposevm()) {
311 *regs
= ext_phy_ctrl_const_base_lpddr2
;
312 *size
= ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2
);
318 const struct dpll_params
*get_dpll_ddr_params(void)
320 int ind
= get_sys_clk_index();
322 if (board_is_eposevm())
323 return &epos_evm_dpll_ddr
[ind
];
324 else if (board_is_evm() || board_is_sk())
325 return &gp_evm_dpll_ddr
;
326 else if (board_is_idk())
327 return &idk_dpll_ddr
;
329 printf(" Board '%s' not supported\n", board_ti_get_name());
336 * Returns the index for safest OPP of the device to boot.
337 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
338 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
339 * This data is read from dev_attribute register which is e-fused.
340 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
341 * OPP available. Lowest OPP starts with min_off. So returning the
342 * bit with rightmost '0'.
344 static int get_opp_offset(int max_off
, int min_off
)
346 struct ctrl_stat
*ctrl
= (struct ctrl_stat
*)CTRL_BASE
;
349 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
350 opp
= readl(&ctrl
->dev_attr
) & ~0xFFFFF000;
352 for (i
= max_off
; i
>= min_off
; i
--) {
353 offset
= opp
& (1 << i
);
361 const struct dpll_params
*get_dpll_mpu_params(void)
363 int opp
= get_opp_offset(DEV_ATTR_MAX_OFFSET
, DEV_ATTR_MIN_OFFSET
);
364 u32 ind
= get_sys_clk_index();
366 return &dpll_mpu
[ind
][opp
];
369 const struct dpll_params
*get_dpll_core_params(void)
371 int ind
= get_sys_clk_index();
373 return &dpll_core
[ind
];
376 const struct dpll_params
*get_dpll_per_params(void)
378 int ind
= get_sys_clk_index();
380 return &dpll_per
[ind
];
383 void scale_vcores_generic(u32 m
)
387 if (i2c_probe(TPS65218_CHIP_PM
))
392 mpu_vdd
= TPS65218_DCDC_VOLT_SEL_1330MV
;
395 mpu_vdd
= TPS65218_DCDC_VOLT_SEL_1260MV
;
398 mpu_vdd
= TPS65218_DCDC_VOLT_SEL_1200MV
;
401 mpu_vdd
= TPS65218_DCDC_VOLT_SEL_1100MV
;
404 mpu_vdd
= TPS65218_DCDC_VOLT_SEL_0950MV
;
407 puts("Unknown MPU clock, not scaling\n");
411 /* Set DCDC1 (CORE) voltage to 1.1V */
412 if (tps65218_voltage_update(TPS65218_DCDC1
,
413 TPS65218_DCDC_VOLT_SEL_1100MV
)) {
414 printf("%s failure\n", __func__
);
418 /* Set DCDC2 (MPU) voltage */
419 if (tps65218_voltage_update(TPS65218_DCDC2
, mpu_vdd
)) {
420 printf("%s failure\n", __func__
);
425 void scale_vcores_idk(u32 m
)
429 if (i2c_probe(TPS62362_I2C_ADDR
))
434 mpu_vdd
= TPS62362_DCDC_VOLT_SEL_1330MV
;
437 mpu_vdd
= TPS62362_DCDC_VOLT_SEL_1260MV
;
440 mpu_vdd
= TPS62362_DCDC_VOLT_SEL_1200MV
;
443 mpu_vdd
= TPS62362_DCDC_VOLT_SEL_1100MV
;
446 mpu_vdd
= TPS62362_DCDC_VOLT_SEL_1330MV
;
449 puts("Unknown MPU clock, not scaling\n");
453 /* Set VDD_MPU voltage */
454 if (tps62362_voltage_update(TPS62362_SET3
, mpu_vdd
)) {
455 printf("%s failure\n", __func__
);
460 void gpi2c_init(void)
462 /* When needed to be invoked prior to BSS initialization */
463 static bool first_time
= true;
466 enable_i2c0_pin_mux();
467 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED
,
468 CONFIG_SYS_OMAP24_I2C_SLAVE
);
473 void scale_vcores(void)
475 const struct dpll_params
*mpu_params
;
477 /* Ensure I2C is initialized for PMIC configuration */
480 /* Get the frequency */
481 mpu_params
= get_dpll_mpu_params();
484 scale_vcores_idk(mpu_params
->m
);
486 scale_vcores_generic(mpu_params
->m
);
489 void set_uart_mux_conf(void)
491 enable_uart0_pin_mux();
494 void set_mux_conf_regs(void)
496 enable_board_pin_mux();
499 static void enable_vtt_regulator(void)
504 writel(GPIO_CTRL_ENABLEMODULE
, AM33XX_GPIO5_BASE
+ OMAP_GPIO_CTRL
);
506 /* enable output for GPIO5_7 */
507 writel(GPIO_SETDATAOUT(7),
508 AM33XX_GPIO5_BASE
+ OMAP_GPIO_SETDATAOUT
);
509 temp
= readl(AM33XX_GPIO5_BASE
+ OMAP_GPIO_OE
);
510 temp
= temp
& ~(GPIO_OE_ENABLE(7));
511 writel(temp
, AM33XX_GPIO5_BASE
+ OMAP_GPIO_OE
);
514 void sdram_init(void)
517 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
518 * GP EMV has 1GB DDR3 connected to EMIF
519 * along with VTT regulator.
521 if (board_is_eposevm()) {
522 config_ddr(0, &ioregs_lpddr2
, NULL
, NULL
, &emif_regs_lpddr2
, 0);
523 } else if (board_is_evm_14_or_later()) {
524 enable_vtt_regulator();
525 config_ddr(0, &ioregs_ddr3
, NULL
, NULL
,
526 &ddr3_emif_regs_400Mhz_production
, 0);
527 } else if (board_is_evm_12_or_later()) {
528 enable_vtt_regulator();
529 config_ddr(0, &ioregs_ddr3
, NULL
, NULL
,
530 &ddr3_emif_regs_400Mhz_beta
, 0);
531 } else if (board_is_evm()) {
532 enable_vtt_regulator();
533 config_ddr(0, &ioregs_ddr3
, NULL
, NULL
,
534 &ddr3_emif_regs_400Mhz
, 0);
535 } else if (board_is_sk()) {
536 config_ddr(400, &ioregs_ddr3
, NULL
, NULL
,
537 &ddr3_sk_emif_regs_400Mhz
, 0);
538 } else if (board_is_idk()) {
539 config_ddr(400, &ioregs_ddr3
, NULL
, NULL
,
540 &ddr3_idk_emif_regs_400Mhz
, 0);
545 /* setup board specific PMIC */
546 int power_init_board(void)
550 if (board_is_idk()) {
551 power_tps62362_init(I2C_PMIC
);
552 p
= pmic_get("TPS62362");
553 if (p
&& !pmic_probe(p
))
554 puts("PMIC: TPS62362\n");
556 power_tps65218_init(I2C_PMIC
);
557 p
= pmic_get("TPS65218_PMIC");
558 if (p
&& !pmic_probe(p
))
559 puts("PMIC: TPS65218\n");
567 struct l3f_cfg_bwlimiter
*bwlimiter
= (struct l3f_cfg_bwlimiter
*)L3F_CFG_BWLIMITER
;
568 u32 mreqprio_0
, mreqprio_1
, modena_init0_bw_fractional
,
569 modena_init0_bw_integer
, modena_init0_watermark_0
;
571 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
574 /* Clear all important bits for DSS errata that may need to be tweaked*/
575 mreqprio_0
= readl(&cdev
->mreqprio_0
) & MREQPRIO_0_SAB_INIT1_MASK
&
576 MREQPRIO_0_SAB_INIT0_MASK
;
578 mreqprio_1
= readl(&cdev
->mreqprio_1
) & MREQPRIO_1_DSS_MASK
;
580 modena_init0_bw_fractional
= readl(&bwlimiter
->modena_init0_bw_fractional
) &
581 BW_LIMITER_BW_FRAC_MASK
;
583 modena_init0_bw_integer
= readl(&bwlimiter
->modena_init0_bw_integer
) &
584 BW_LIMITER_BW_INT_MASK
;
586 modena_init0_watermark_0
= readl(&bwlimiter
->modena_init0_watermark_0
) &
587 BW_LIMITER_BW_WATERMARK_MASK
;
589 /* Setting MReq Priority of the DSS*/
593 * Set L3 Fast Configuration Register
594 * Limiting bandwith for ARM core to 700 MBPS
596 modena_init0_bw_fractional
|= 0x10;
597 modena_init0_bw_integer
|= 0x3;
599 writel(mreqprio_0
, &cdev
->mreqprio_0
);
600 writel(mreqprio_1
, &cdev
->mreqprio_1
);
602 writel(modena_init0_bw_fractional
, &bwlimiter
->modena_init0_bw_fractional
);
603 writel(modena_init0_bw_integer
, &bwlimiter
->modena_init0_bw_integer
);
604 writel(modena_init0_watermark_0
, &bwlimiter
->modena_init0_watermark_0
);
609 #ifdef CONFIG_BOARD_LATE_INIT
610 int board_late_init(void)
612 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
613 set_board_info_env(NULL
);
616 * Default FIT boot on HS devices. Non FIT images are not allowed
619 if (get_device_type() == HS_DEVICE
)
620 setenv("boot_fit", "1");
626 #ifdef CONFIG_USB_DWC3
627 static struct dwc3_device usb_otg_ss1
= {
628 .maximum_speed
= USB_SPEED_HIGH
,
629 .base
= USB_OTG_SS1_BASE
,
630 .tx_fifo_resize
= false,
634 static struct dwc3_omap_device usb_otg_ss1_glue
= {
635 .base
= (void *)USB_OTG_SS1_GLUE_BASE
,
636 .utmi_mode
= DWC3_OMAP_UTMI_MODE_SW
,
640 static struct ti_usb_phy_device usb_phy1_device
= {
641 .usb2_phy_power
= (void *)USB2_PHY1_POWER
,
645 static struct dwc3_device usb_otg_ss2
= {
646 .maximum_speed
= USB_SPEED_HIGH
,
647 .base
= USB_OTG_SS2_BASE
,
648 .tx_fifo_resize
= false,
652 static struct dwc3_omap_device usb_otg_ss2_glue
= {
653 .base
= (void *)USB_OTG_SS2_GLUE_BASE
,
654 .utmi_mode
= DWC3_OMAP_UTMI_MODE_SW
,
658 static struct ti_usb_phy_device usb_phy2_device
= {
659 .usb2_phy_power
= (void *)USB2_PHY2_POWER
,
663 int usb_gadget_handle_interrupts(int index
)
667 status
= dwc3_omap_uboot_interrupt_status(index
);
669 dwc3_uboot_handle_interrupt(index
);
673 #endif /* CONFIG_USB_DWC3 */
675 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
676 int omap_xhci_board_usb_init(int index
, enum usb_init_type init
)
678 enable_usb_clocks(index
);
679 #ifdef CONFIG_USB_DWC3
682 if (init
== USB_INIT_DEVICE
) {
683 usb_otg_ss1
.dr_mode
= USB_DR_MODE_PERIPHERAL
;
684 usb_otg_ss1_glue
.vbus_id_status
= OMAP_DWC3_VBUS_VALID
;
685 dwc3_omap_uboot_init(&usb_otg_ss1_glue
);
686 ti_usb_phy_uboot_init(&usb_phy1_device
);
687 dwc3_uboot_init(&usb_otg_ss1
);
691 if (init
== USB_INIT_DEVICE
) {
692 usb_otg_ss2
.dr_mode
= USB_DR_MODE_PERIPHERAL
;
693 usb_otg_ss2_glue
.vbus_id_status
= OMAP_DWC3_VBUS_VALID
;
694 ti_usb_phy_uboot_init(&usb_phy2_device
);
695 dwc3_omap_uboot_init(&usb_otg_ss2_glue
);
696 dwc3_uboot_init(&usb_otg_ss2
);
700 printf("Invalid Controller Index\n");
707 int omap_xhci_board_usb_cleanup(int index
, enum usb_init_type init
)
709 #ifdef CONFIG_USB_DWC3
713 if (init
== USB_INIT_DEVICE
) {
714 ti_usb_phy_uboot_exit(index
);
715 dwc3_uboot_exit(index
);
716 dwc3_omap_uboot_exit(index
);
720 printf("Invalid Controller Index\n");
723 disable_usb_clocks(index
);
727 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
729 #ifdef CONFIG_DRIVER_TI_CPSW
731 static void cpsw_control(int enabled
)
733 /* Additional controls can be added here */
737 static struct cpsw_slave_data cpsw_slaves
[] = {
739 .slave_reg_ofs
= 0x208,
740 .sliver_reg_ofs
= 0xd80,
744 .slave_reg_ofs
= 0x308,
745 .sliver_reg_ofs
= 0xdc0,
750 static struct cpsw_platform_data cpsw_data
= {
751 .mdio_base
= CPSW_MDIO_BASE
,
752 .cpsw_base
= CPSW_BASE
,
755 .cpdma_reg_ofs
= 0x800,
757 .slave_data
= cpsw_slaves
,
758 .ale_reg_ofs
= 0xd00,
760 .host_port_reg_ofs
= 0x108,
761 .hw_stats_reg_ofs
= 0x900,
762 .bd_ram_ofs
= 0x2000,
763 .mac_control
= (1 << 5),
764 .control
= cpsw_control
,
766 .version
= CPSW_CTRL_VERSION_2
,
769 int board_eth_init(bd_t
*bis
)
773 uint32_t mac_hi
, mac_lo
;
775 /* try reading mac address from efuse */
776 mac_lo
= readl(&cdev
->macid0l
);
777 mac_hi
= readl(&cdev
->macid0h
);
778 mac_addr
[0] = mac_hi
& 0xFF;
779 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
780 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
781 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
782 mac_addr
[4] = mac_lo
& 0xFF;
783 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
785 if (!getenv("ethaddr")) {
786 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
787 if (is_valid_ethaddr(mac_addr
))
788 eth_setenv_enetaddr("ethaddr", mac_addr
);
791 mac_lo
= readl(&cdev
->macid1l
);
792 mac_hi
= readl(&cdev
->macid1h
);
793 mac_addr
[0] = mac_hi
& 0xFF;
794 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
795 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
796 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
797 mac_addr
[4] = mac_lo
& 0xFF;
798 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
800 if (!getenv("eth1addr")) {
801 if (is_valid_ethaddr(mac_addr
))
802 eth_setenv_enetaddr("eth1addr", mac_addr
);
805 if (board_is_eposevm()) {
806 writel(RMII_MODE_ENABLE
| RMII_CHIPCKL_ENABLE
, &cdev
->miisel
);
807 cpsw_slaves
[0].phy_if
= PHY_INTERFACE_MODE_RMII
;
808 cpsw_slaves
[0].phy_addr
= 16;
809 } else if (board_is_sk()) {
810 writel(RGMII_MODE_ENABLE
, &cdev
->miisel
);
811 cpsw_slaves
[0].phy_if
= PHY_INTERFACE_MODE_RGMII
;
812 cpsw_slaves
[0].phy_addr
= 4;
813 cpsw_slaves
[1].phy_addr
= 5;
814 } else if (board_is_idk()) {
815 writel(RGMII_MODE_ENABLE
, &cdev
->miisel
);
816 cpsw_slaves
[0].phy_if
= PHY_INTERFACE_MODE_RGMII
;
817 cpsw_slaves
[0].phy_addr
= 0;
819 writel(RGMII_MODE_ENABLE
, &cdev
->miisel
);
820 cpsw_slaves
[0].phy_if
= PHY_INTERFACE_MODE_RGMII
;
821 cpsw_slaves
[0].phy_addr
= 0;
824 rv
= cpsw_register(&cpsw_data
);
826 printf("Error %d registering CPSW switch\n", rv
);
832 #ifdef CONFIG_SPL_LOAD_FIT
833 int board_fit_config_name_match(const char *name
)
835 if (board_is_evm() && !strcmp(name
, "am437x-gp-evm"))
837 else if (board_is_sk() && !strcmp(name
, "am437x-sk-evm"))
839 else if (board_is_eposevm() && !strcmp(name
, "am43x-epos-evm"))
841 else if (board_is_idk() && !strcmp(name
, "am437x-idk-evm"))
848 #ifdef CONFIG_TI_SECURE_DEVICE
849 void board_fit_image_post_process(void **p_image
, size_t *p_size
)
851 secure_boot_verify_image(p_image
, p_size
);