board/ti/am43xx/mux.c

   1 /*
   2  * mux.c
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/arch/mux.h>
  12 #include "board.h"
  13
  14 static struct module_pin_mux rmii1_pin_mux[] = {
  15         {OFFSET(mii1_txen), MODE(1)},                   /* RMII1_TXEN */
  16         {OFFSET(mii1_txd1), MODE(1)},                   /* RMII1_TD1 */
  17         {OFFSET(mii1_txd0), MODE(1)},                   /* RMII1_TD0 */
  18         {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},        /* RMII1_RD1 */
  19         {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},        /* RMII1_RD0 */
  20         {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE},        /* RMII1_RXDV */
  21         {OFFSET(mii1_crs), MODE(1) | RXACTIVE},         /* RMII1_CRS_DV */
  22         {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},       /* RMII1_RXERR */
  23         {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},     /* RMII1_refclk */
  24         {-1},
  25 };
  26
  27 static struct module_pin_mux rgmii1_pin_mux[] = {
  28         {OFFSET(mii1_txen), MODE(2)},                   /* RGMII1_TCTL */
  29         {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},        /* RGMII1_RCTL */
  30         {OFFSET(mii1_txd3), MODE(2)},                   /* RGMII1_TD3 */
  31         {OFFSET(mii1_txd2), MODE(2)},                   /* RGMII1_TD2 */
  32         {OFFSET(mii1_txd1), MODE(2)},                   /* RGMII1_TD1 */
  33         {OFFSET(mii1_txd0), MODE(2)},                   /* RGMII1_TD0 */
  34         {OFFSET(mii1_txclk), MODE(2)},                  /* RGMII1_TCLK */
  35         {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},       /* RGMII1_RCLK */
  36         {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},        /* RGMII1_RD3 */
  37         {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},        /* RGMII1_RD2 */
  38         {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},        /* RGMII1_RD1 */
  39         {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},        /* RGMII1_RD0 */
  40         {-1},
  41 };
  42
  43 static struct module_pin_mux mdio_pin_mux[] = {
  44         {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
  45         {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK */
  46         {-1},
  47 };
  48
  49 static struct module_pin_mux uart0_pin_mux[] = {
  50         {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
  51         {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
  52         {-1},
  53 };
  54
  55 static struct module_pin_mux mmc0_pin_mux[] = {
  56         {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)},  /* MMC0_CLK */
  57         {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* MMC0_CMD */
  58         {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */
  59         {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */
  60         {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */
  61         {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */
  62         {-1},
  63 };
  64
  65 static struct module_pin_mux i2c0_pin_mux[] = {
  66         {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
  67         {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
  68         {-1},
  69 };
  70
  71 static struct module_pin_mux gpio5_7_pin_mux[] = {
  72         {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)},      /* GPIO5_7 */
  73         {-1},
  74 };
  75
  76 static struct module_pin_mux qspi_pin_mux[] = {
  77         {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
  78         {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
  79         {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
  80         {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
  81         {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
  82         {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
  83         {-1},
  84 };
  85
  86 void enable_uart0_pin_mux(void)
  87 {
  88         configure_module_pin_mux(uart0_pin_mux);
  89 }
  90
  91 void enable_board_pin_mux(void)
  92 {
  93         configure_module_pin_mux(mmc0_pin_mux);
  94         configure_module_pin_mux(i2c0_pin_mux);
  95         configure_module_pin_mux(mdio_pin_mux);
  96
  97         if (board_is_gpevm()) {
  98                 configure_module_pin_mux(gpio5_7_pin_mux);
  99                 configure_module_pin_mux(rgmii1_pin_mux);
 100         } else if (board_is_sk()) {
 101                 configure_module_pin_mux(rgmii1_pin_mux);
 102                 configure_module_pin_mux(qspi_pin_mux);
 103         } else if (board_is_eposevm()) {
 104                 configure_module_pin_mux(rmii1_pin_mux);
 105                 configure_module_pin_mux(qspi_pin_mux);
 106         }
 107 }
 108
 109 void enable_i2c0_pin_mux(void)
 110 {
 111         configure_module_pin_mux(i2c0_pin_mux);
 112 }