2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/dra7xx_iodelay.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sata.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/omap.h>
26 #include <environment.h>
28 #include <linux/usb/gadget.h>
29 #include <dwc3-uboot.h>
30 #include <dwc3-omap-uboot.h>
31 #include <ti-usb-phy-uboot.h>
33 #include "../common/board_detect.h"
36 #define board_is_x15() board_ti_is("BBRDX15_")
37 #define board_is_am572x_evm() board_ti_is("AM572PM_")
39 #ifdef CONFIG_DRIVER_TI_CPSW
43 DECLARE_GLOBAL_DATA_PTR
;
46 #define GPIO_DDR_VTT_EN 203
48 #define SYSINFO_BOARD_NAME_MAX_LEN 45
50 const struct omap_sysinfo sysinfo
= {
51 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
54 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs
= {
55 .dmm_lisa_map_3
= 0x80740300,
59 void emif_get_dmm_regs(const struct dmm_lisa_map_regs
**dmm_lisa_regs
)
61 *dmm_lisa_regs
= &beagle_x15_lisa_regs
;
64 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs
= {
65 .sdram_config_init
= 0x61851b32,
66 .sdram_config
= 0x61851b32,
67 .sdram_config2
= 0x08000000,
68 .ref_ctrl
= 0x000040F1,
69 .ref_ctrl_final
= 0x00001035,
70 .sdram_tim1
= 0xcccf36ab,
71 .sdram_tim2
= 0x308f7fda,
72 .sdram_tim3
= 0x409f88a8,
73 .read_idle_ctrl
= 0x00050000,
74 .zq_config
= 0x5007190b,
75 .temp_alert_config
= 0x00000000,
76 .emif_ddr_phy_ctlr_1_init
= 0x0024400b,
77 .emif_ddr_phy_ctlr_1
= 0x0e24400b,
78 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
79 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
80 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
81 .emif_ddr_ext_phy_ctrl_4
= 0x009b009b,
82 .emif_ddr_ext_phy_ctrl_5
= 0x009e009e,
83 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
84 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
85 .emif_rd_wr_lvl_ctl
= 0x00000000,
86 .emif_rd_wr_exec_thresh
= 0x00000305
89 /* Ext phy ctrl regs 1-35 */
90 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs
[] = {
128 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs
= {
129 .sdram_config_init
= 0x61851b32,
130 .sdram_config
= 0x61851b32,
131 .sdram_config2
= 0x08000000,
132 .ref_ctrl
= 0x000040F1,
133 .ref_ctrl_final
= 0x00001035,
134 .sdram_tim1
= 0xcccf36ab,
135 .sdram_tim2
= 0x308f7fda,
136 .sdram_tim3
= 0x409f88a8,
137 .read_idle_ctrl
= 0x00050000,
138 .zq_config
= 0x5007190b,
139 .temp_alert_config
= 0x00000000,
140 .emif_ddr_phy_ctlr_1_init
= 0x0024400b,
141 .emif_ddr_phy_ctlr_1
= 0x0e24400b,
142 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
143 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
144 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
145 .emif_ddr_ext_phy_ctrl_4
= 0x009b009b,
146 .emif_ddr_ext_phy_ctrl_5
= 0x009e009e,
147 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
148 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
149 .emif_rd_wr_lvl_ctl
= 0x00000000,
150 .emif_rd_wr_exec_thresh
= 0x00000305
153 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs
[] = {
191 void emif_get_reg_dump(u32 emif_nr
, const struct emif_regs
**regs
)
195 *regs
= &beagle_x15_emif1_ddr3_532mhz_emif_regs
;
198 *regs
= &beagle_x15_emif2_ddr3_532mhz_emif_regs
;
203 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr
, const u32
**regs
, u32
*size
)
207 *regs
= beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs
;
208 *size
= ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs
);
211 *regs
= beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs
;
212 *size
= ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs
);
217 struct vcores_data beagle_x15_volts
= {
218 .mpu
.value
= VDD_MPU_DRA752
,
219 .mpu
.efuse
.reg
= STD_FUSE_OPP_VMIN_MPU_NOM
,
220 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
221 .mpu
.addr
= TPS659038_REG_ADDR_SMPS12
,
222 .mpu
.pmic
= &tps659038
,
224 .eve
.value
= VDD_EVE_DRA752
,
225 .eve
.efuse
.reg
= STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
226 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
227 .eve
.addr
= TPS659038_REG_ADDR_SMPS45
,
228 .eve
.pmic
= &tps659038
,
230 .gpu
.value
= VDD_GPU_DRA752
,
231 .gpu
.efuse
.reg
= STD_FUSE_OPP_VMIN_GPU_NOM
,
232 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
233 .gpu
.addr
= TPS659038_REG_ADDR_SMPS45
,
234 .gpu
.pmic
= &tps659038
,
236 .core
.value
= VDD_CORE_DRA752
,
237 .core
.efuse
.reg
= STD_FUSE_OPP_VMIN_CORE_NOM
,
238 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
239 .core
.addr
= TPS659038_REG_ADDR_SMPS6
,
240 .core
.pmic
= &tps659038
,
242 .iva
.value
= VDD_IVA_DRA752
,
243 .iva
.efuse
.reg
= STD_FUSE_OPP_VMIN_IVA_NOM
,
244 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
245 .iva
.addr
= TPS659038_REG_ADDR_SMPS45
,
246 .iva
.pmic
= &tps659038
,
249 #ifdef CONFIG_SPL_BUILD
250 /* No env to setup for SPL */
251 static inline void setup_board_eeprom_env(void) { }
253 /* Override function to read eeprom information */
254 void do_board_detect(void)
258 rc
= ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
259 CONFIG_EEPROM_CHIP_ADDRESS
);
261 printf("ti_i2c_eeprom_init failed %d\n", rc
);
264 #else /* CONFIG_SPL_BUILD */
266 /* Override function to read eeprom information: actual i2c read done by SPL*/
267 void do_board_detect(void)
272 rc
= ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
273 CONFIG_EEPROM_CHIP_ADDRESS
);
275 printf("ti_i2c_eeprom_init failed %d\n", rc
);
278 bname
= "BeagleBoard X15";
279 else if (board_is_am572x_evm())
280 bname
= "AM572x EVM";
283 snprintf(sysinfo
.board_string
, SYSINFO_BOARD_NAME_MAX_LEN
,
284 "Board: %s REV %s\n", bname
, board_ti_get_rev());
287 static void setup_board_eeprom_env(void)
289 char *name
= "beagle_x15";
292 rc
= ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
293 CONFIG_EEPROM_CHIP_ADDRESS
);
297 if (board_is_am572x_evm())
300 printf("Unidentified board claims %s in eeprom header\n",
301 board_ti_get_name());
304 set_board_info_env(name
);
307 #endif /* CONFIG_SPL_BUILD */
309 void hw_data_init(void)
311 *prcm
= &dra7xx_prcm
;
312 *dplls_data
= &dra7xx_dplls
;
313 *omap_vcores
= &beagle_x15_volts
;
314 *ctrl
= &dra7xx_ctrl
;
320 gd
->bd
->bi_boot_params
= (CONFIG_SYS_SDRAM_BASE
+ 0x100);
325 int board_late_init(void)
327 setup_board_eeprom_env();
330 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
331 * This is the POWERHOLD-in-Low behavior.
333 palmas_i2c_write_u8(TPS65903X_CHIP_P1
, 0xA0, 0x1);
337 void set_muxconf_regs(void)
339 do_set_mux32((*ctrl
)->control_padconf_core_base
,
340 early_padconf
, ARRAY_SIZE(early_padconf
));
343 #ifdef CONFIG_IODELAY_RECALIBRATION
344 void recalibrate_iodelay(void)
346 __recalibrate_iodelay(core_padconf_array_essential
,
347 ARRAY_SIZE(core_padconf_array_essential
),
348 iodelay_cfg_array
, ARRAY_SIZE(iodelay_cfg_array
));
352 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
353 int board_mmc_init(bd_t
*bis
)
355 omap_mmc_init(0, 0, 0, -1, -1);
356 omap_mmc_init(1, 0, 0, -1, -1);
361 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
362 int spl_start_uboot(void)
364 /* break into full u-boot on 'c' */
365 if (serial_tstc() && serial_getc() == 'c')
368 #ifdef CONFIG_SPL_ENV_SUPPORT
371 if (getenv_yesno("boot_os") != 1)
379 #ifdef CONFIG_USB_DWC3
380 static struct dwc3_device usb_otg_ss1
= {
381 .maximum_speed
= USB_SPEED_SUPER
,
382 .base
= DRA7_USB_OTG_SS1_BASE
,
383 .tx_fifo_resize
= false,
387 static struct dwc3_omap_device usb_otg_ss1_glue
= {
388 .base
= (void *)DRA7_USB_OTG_SS1_GLUE_BASE
,
389 .utmi_mode
= DWC3_OMAP_UTMI_MODE_SW
,
393 static struct ti_usb_phy_device usb_phy1_device
= {
394 .pll_ctrl_base
= (void *)DRA7_USB3_PHY1_PLL_CTRL
,
395 .usb2_phy_power
= (void *)DRA7_USB2_PHY1_POWER
,
396 .usb3_phy_power
= (void *)DRA7_USB3_PHY1_POWER
,
400 static struct dwc3_device usb_otg_ss2
= {
401 .maximum_speed
= USB_SPEED_HIGH
,
402 .base
= DRA7_USB_OTG_SS2_BASE
,
403 .tx_fifo_resize
= false,
407 static struct dwc3_omap_device usb_otg_ss2_glue
= {
408 .base
= (void *)DRA7_USB_OTG_SS2_GLUE_BASE
,
409 .utmi_mode
= DWC3_OMAP_UTMI_MODE_SW
,
413 static struct ti_usb_phy_device usb_phy2_device
= {
414 .usb2_phy_power
= (void *)DRA7_USB2_PHY2_POWER
,
418 int board_usb_init(int index
, enum usb_init_type init
)
420 enable_usb_clocks(index
);
423 if (init
== USB_INIT_DEVICE
) {
424 printf("port %d can't be used as device\n", index
);
425 disable_usb_clocks(index
);
428 usb_otg_ss1
.dr_mode
= USB_DR_MODE_HOST
;
429 usb_otg_ss1_glue
.vbus_id_status
= OMAP_DWC3_ID_GROUND
;
430 setbits_le32((*prcm
)->cm_l3init_usb_otg_ss1_clkctrl
,
431 OTG_SS_CLKCTRL_MODULEMODE_HW
|
432 OPTFCLKEN_REFCLK960M
);
435 ti_usb_phy_uboot_init(&usb_phy1_device
);
436 dwc3_omap_uboot_init(&usb_otg_ss1_glue
);
437 dwc3_uboot_init(&usb_otg_ss1
);
440 if (init
== USB_INIT_DEVICE
) {
441 usb_otg_ss2
.dr_mode
= USB_DR_MODE_PERIPHERAL
;
442 usb_otg_ss2_glue
.vbus_id_status
= OMAP_DWC3_VBUS_VALID
;
444 printf("port %d can't be used as host\n", index
);
445 disable_usb_clocks(index
);
449 ti_usb_phy_uboot_init(&usb_phy2_device
);
450 dwc3_omap_uboot_init(&usb_otg_ss2_glue
);
451 dwc3_uboot_init(&usb_otg_ss2
);
454 printf("Invalid Controller Index\n");
460 int board_usb_cleanup(int index
, enum usb_init_type init
)
465 ti_usb_phy_uboot_exit(index
);
466 dwc3_uboot_exit(index
);
467 dwc3_omap_uboot_exit(index
);
470 printf("Invalid Controller Index\n");
472 disable_usb_clocks(index
);
476 int usb_gadget_handle_interrupts(int index
)
480 status
= dwc3_omap_uboot_interrupt_status(index
);
482 dwc3_uboot_handle_interrupt(index
);
488 #ifdef CONFIG_DRIVER_TI_CPSW
490 /* Delay value to add to calibrated value */
491 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
492 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
493 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
494 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
495 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
496 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
497 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
498 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
499 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
500 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
502 static void cpsw_control(int enabled
)
504 /* VTP can be added here */
507 static struct cpsw_slave_data cpsw_slaves
[] = {
509 .slave_reg_ofs
= 0x208,
510 .sliver_reg_ofs
= 0xd80,
514 .slave_reg_ofs
= 0x308,
515 .sliver_reg_ofs
= 0xdc0,
520 static struct cpsw_platform_data cpsw_data
= {
521 .mdio_base
= CPSW_MDIO_BASE
,
522 .cpsw_base
= CPSW_BASE
,
525 .cpdma_reg_ofs
= 0x800,
527 .slave_data
= cpsw_slaves
,
528 .ale_reg_ofs
= 0xd00,
530 .host_port_reg_ofs
= 0x108,
531 .hw_stats_reg_ofs
= 0x900,
532 .bd_ram_ofs
= 0x2000,
533 .mac_control
= (1 << 5),
534 .control
= cpsw_control
,
536 .version
= CPSW_CTRL_VERSION_2
,
539 static u64
mac_to_u64(u8 mac
[6])
544 for (i
= 0; i
< 6; i
++) {
552 static void u64_to_mac(u64 addr
, u8 mac
[6])
562 int board_eth_init(bd_t
*bis
)
566 uint32_t mac_hi
, mac_lo
;
570 u8 mac_addr1
[6], mac_addr2
[6];
573 /* try reading mac address from efuse */
574 mac_lo
= readl((*ctrl
)->control_core_mac_id_0_lo
);
575 mac_hi
= readl((*ctrl
)->control_core_mac_id_0_hi
);
576 mac_addr
[0] = (mac_hi
& 0xFF0000) >> 16;
577 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
578 mac_addr
[2] = mac_hi
& 0xFF;
579 mac_addr
[3] = (mac_lo
& 0xFF0000) >> 16;
580 mac_addr
[4] = (mac_lo
& 0xFF00) >> 8;
581 mac_addr
[5] = mac_lo
& 0xFF;
583 if (!getenv("ethaddr")) {
584 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
586 if (is_valid_ethaddr(mac_addr
))
587 eth_setenv_enetaddr("ethaddr", mac_addr
);
590 mac_lo
= readl((*ctrl
)->control_core_mac_id_1_lo
);
591 mac_hi
= readl((*ctrl
)->control_core_mac_id_1_hi
);
592 mac_addr
[0] = (mac_hi
& 0xFF0000) >> 16;
593 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
594 mac_addr
[2] = mac_hi
& 0xFF;
595 mac_addr
[3] = (mac_lo
& 0xFF0000) >> 16;
596 mac_addr
[4] = (mac_lo
& 0xFF00) >> 8;
597 mac_addr
[5] = mac_lo
& 0xFF;
599 if (!getenv("eth1addr")) {
600 if (is_valid_ethaddr(mac_addr
))
601 eth_setenv_enetaddr("eth1addr", mac_addr
);
604 ctrl_val
= readl((*ctrl
)->control_core_control_io1
) & (~0x33);
606 writel(ctrl_val
, (*ctrl
)->control_core_control_io1
);
608 ret
= cpsw_register(&cpsw_data
);
610 printf("Error %d registering CPSW switch\n", ret
);
613 * Export any Ethernet MAC addresses from EEPROM.
614 * On AM57xx the 2 MAC addresses define the address range
616 board_ti_get_eth_mac_addr(0, mac_addr1
);
617 board_ti_get_eth_mac_addr(1, mac_addr2
);
619 if (is_valid_ethaddr(mac_addr1
) && is_valid_ethaddr(mac_addr2
)) {
620 mac1
= mac_to_u64(mac_addr1
);
621 mac2
= mac_to_u64(mac_addr2
);
623 /* must contain an address range */
624 num_macs
= mac2
- mac1
+ 1;
625 /* <= 50 to protect against user programming error */
626 if (num_macs
> 0 && num_macs
<= 50) {
627 for (i
= 0; i
< num_macs
; i
++) {
628 u64_to_mac(mac1
+ i
, mac_addr
);
629 if (is_valid_ethaddr(mac_addr
)) {
630 eth_setenv_enetaddr_by_index("eth",
642 #ifdef CONFIG_BOARD_EARLY_INIT_F
643 /* VTT regulator enable */
644 static inline void vtt_regulator_enable(void)
646 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL
)
649 gpio_request(GPIO_DDR_VTT_EN
, "ddr_vtt_en");
650 gpio_direction_output(GPIO_DDR_VTT_EN
, 1);
653 int board_early_init_f(void)
655 vtt_regulator_enable();