board/ti/evm/evm.h

   1 /*
   2  * (C) Copyright 2008
   3  * Nishanth Menon <menon.nishanth@gmail.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #ifndef _EVM_H_
  24 #define _EVM_H_
  25
  26 const omap3_sysinfo sysinfo = {
  27         DDR_DISCRETE,
  28         "OMAP3 EVM board",
  29 #if defined(CONFIG_ENV_IS_IN_ONENAND)
  30         "OneNAND",
  31 #else
  32         "NAND",
  33 #endif
  34 };
  35
  36 /*
  37  * OMAP35x EVM revision
  38  * Run time detection of EVM revision is done by reading Ethernet
  39  * PHY ID -
  40  *      GEN_1   = 0x01150000
  41  *      GEN_2   = 0x92200000
  42  */
  43 enum {
  44         OMAP3EVM_BOARD_GEN_1 = 0,       /* EVM Rev between  A - D */
  45         OMAP3EVM_BOARD_GEN_2,           /* EVM Rev >= Rev E */
  46 };
  47
  48 u8 get_omap3_evm_rev(void);
  49
  50 static void setup_net_chip(void);
  51
  52 /*
  53  * IEN  - Input Enable
  54  * IDIS - Input Disable
  55  * PTD  - Pull type Down
  56  * PTU  - Pull type Up
  57  * DIS  - Pull type selection is inactive
  58  * EN   - Pull type selection is active
  59  * M0   - Mode 0
  60  * The commented string gives the final mux configuration for that pin
  61  */
  62 #define MUX_EVM() \
  63  /*SDRC*/\
  64         MUX_VAL(CP(SDRC_D0),            (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
  65         MUX_VAL(CP(SDRC_D1),            (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
  66         MUX_VAL(CP(SDRC_D2),            (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
  67         MUX_VAL(CP(SDRC_D3),            (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
  68         MUX_VAL(CP(SDRC_D4),            (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
  69         MUX_VAL(CP(SDRC_D5),            (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
  70         MUX_VAL(CP(SDRC_D6),            (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
  71         MUX_VAL(CP(SDRC_D7),            (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
  72         MUX_VAL(CP(SDRC_D8),            (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
  73         MUX_VAL(CP(SDRC_D9),            (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
  74         MUX_VAL(CP(SDRC_D10),           (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
  75         MUX_VAL(CP(SDRC_D11),           (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
  76         MUX_VAL(CP(SDRC_D12),           (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
  77         MUX_VAL(CP(SDRC_D13),           (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
  78         MUX_VAL(CP(SDRC_D14),           (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
  79         MUX_VAL(CP(SDRC_D15),           (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
  80         MUX_VAL(CP(SDRC_D16),           (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
  81         MUX_VAL(CP(SDRC_D17),           (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
  82         MUX_VAL(CP(SDRC_D18),           (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
  83         MUX_VAL(CP(SDRC_D19),           (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
  84         MUX_VAL(CP(SDRC_D20),           (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
  85         MUX_VAL(CP(SDRC_D21),           (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
  86         MUX_VAL(CP(SDRC_D22),           (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
  87         MUX_VAL(CP(SDRC_D23),           (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
  88         MUX_VAL(CP(SDRC_D24),           (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
  89         MUX_VAL(CP(SDRC_D25),           (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
  90         MUX_VAL(CP(SDRC_D26),           (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
  91         MUX_VAL(CP(SDRC_D27),           (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
  92         MUX_VAL(CP(SDRC_D28),           (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
  93         MUX_VAL(CP(SDRC_D29),           (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
  94         MUX_VAL(CP(SDRC_D30),           (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
  95         MUX_VAL(CP(SDRC_D31),           (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
  96         MUX_VAL(CP(SDRC_CLK),           (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
  97         MUX_VAL(CP(SDRC_DQS0),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
  98         MUX_VAL(CP(SDRC_DQS1),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
  99         MUX_VAL(CP(SDRC_DQS2),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
 100         MUX_VAL(CP(SDRC_DQS3),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
 101  /*GPMC*/\
 102         MUX_VAL(CP(GPMC_A1),            (IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
 103         MUX_VAL(CP(GPMC_A2),            (IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
 104         MUX_VAL(CP(GPMC_A3),            (IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
 105         MUX_VAL(CP(GPMC_A4),            (IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
 106         MUX_VAL(CP(GPMC_A5),            (IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
 107         MUX_VAL(CP(GPMC_A6),            (IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
 108         MUX_VAL(CP(GPMC_A7),            (IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
 109         MUX_VAL(CP(GPMC_A8),            (IDIS | PTU | EN  | M0)) /*GPMC_A8*/\
 110         MUX_VAL(CP(GPMC_A9),            (IDIS | PTU | EN  | M0)) /*GPMC_A9*/\
 111         MUX_VAL(CP(GPMC_A10),           (IDIS | PTU | EN  | M0)) /*GPMC_A10*/\
 112         MUX_VAL(CP(GPMC_D0),            (IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
 113         MUX_VAL(CP(GPMC_D1),            (IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
 114         MUX_VAL(CP(GPMC_D2),            (IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
 115         MUX_VAL(CP(GPMC_D3),            (IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
 116         MUX_VAL(CP(GPMC_D4),            (IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
 117         MUX_VAL(CP(GPMC_D5),            (IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
 118         MUX_VAL(CP(GPMC_D6),            (IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
 119         MUX_VAL(CP(GPMC_D7),            (IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
 120         MUX_VAL(CP(GPMC_D8),            (IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
 121         MUX_VAL(CP(GPMC_D9),            (IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
 122         MUX_VAL(CP(GPMC_D10),           (IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
 123         MUX_VAL(CP(GPMC_D11),           (IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
 124         MUX_VAL(CP(GPMC_D12),           (IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
 125         MUX_VAL(CP(GPMC_D13),           (IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
 126         MUX_VAL(CP(GPMC_D14),           (IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
 127         MUX_VAL(CP(GPMC_D15),           (IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
 128         MUX_VAL(CP(GPMC_NCS0),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
 129         MUX_VAL(CP(GPMC_NCS1),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
 130         MUX_VAL(CP(GPMC_NCS2),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
 131         MUX_VAL(CP(GPMC_NCS3),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
 132         MUX_VAL(CP(GPMC_NCS4),          (IEN  | PTU | EN  | M0)) /*GPMC_nCS4*/\
 133         MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
 134         MUX_VAL(CP(GPMC_NCS6),          (IEN  | PTD | DIS | M0)) /*GPMC_nCS6*/\
 135         MUX_VAL(CP(GPMC_NCS7),          (IEN  | PTU | EN  | M0)) /*GPMC_nCS7*/\
 136         MUX_VAL(CP(GPMC_CLK),           (IDIS | PTU | EN  | M0)) /*GPMC_CLK*/\
 137         MUX_VAL(CP(GPMC_NADV_ALE),      (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
 138         MUX_VAL(CP(GPMC_NOE),           (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
 139         MUX_VAL(CP(GPMC_NWE),           (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
 140         MUX_VAL(CP(GPMC_NBE0_CLE),      (IDIS | PTU | EN  | M0)) /*GPMC_nBE0_CLE*/\
 141         MUX_VAL(CP(GPMC_NBE1),          (IEN  | PTU | EN  | M0)) /*GPMC_nBE1*/\
 142         MUX_VAL(CP(GPMC_NWP),           (IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
 143         MUX_VAL(CP(GPMC_WAIT0),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
 144         MUX_VAL(CP(GPMC_WAIT1),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
 145         MUX_VAL(CP(GPMC_WAIT2),         (IEN  | PTU | EN  | M4)) /*GPIO_64*/\
 146                                                                  /* - ETH_nRESET*/\
 147         MUX_VAL(CP(GPMC_WAIT3),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
 148  /*DSS*/\
 149         MUX_VAL(CP(DSS_PCLK),           (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
 150         MUX_VAL(CP(DSS_HSYNC),          (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
 151         MUX_VAL(CP(DSS_VSYNC),          (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
 152         MUX_VAL(CP(DSS_ACBIAS),         (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
 153         MUX_VAL(CP(DSS_DATA0),          (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
 154         MUX_VAL(CP(DSS_DATA1),          (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
 155         MUX_VAL(CP(DSS_DATA2),          (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
 156         MUX_VAL(CP(DSS_DATA3),          (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
 157         MUX_VAL(CP(DSS_DATA4),          (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
 158         MUX_VAL(CP(DSS_DATA5),          (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
 159         MUX_VAL(CP(DSS_DATA6),          (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
 160         MUX_VAL(CP(DSS_DATA7),          (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
 161         MUX_VAL(CP(DSS_DATA8),          (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
 162         MUX_VAL(CP(DSS_DATA9),          (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
 163         MUX_VAL(CP(DSS_DATA10),         (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
 164         MUX_VAL(CP(DSS_DATA11),         (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
 165         MUX_VAL(CP(DSS_DATA12),         (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
 166         MUX_VAL(CP(DSS_DATA13),         (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
 167         MUX_VAL(CP(DSS_DATA14),         (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
 168         MUX_VAL(CP(DSS_DATA15),         (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
 169         MUX_VAL(CP(DSS_DATA16),         (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
 170         MUX_VAL(CP(DSS_DATA17),         (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
 171         MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
 172         MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
 173         MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
 174         MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
 175         MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
 176         MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
 177  /*CAMERA*/\
 178         MUX_VAL(CP(CAM_HS),             (IEN  | PTU | EN  | M0)) /*CAM_HS */\
 179         MUX_VAL(CP(CAM_VS),             (IEN  | PTU | EN  | M0)) /*CAM_VS */\
 180         MUX_VAL(CP(CAM_XCLKA),          (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
 181         MUX_VAL(CP(CAM_PCLK),           (IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
 182         MUX_VAL(CP(CAM_FLD),            (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
 183                                                                  /* - CAM_RESET*/\
 184         MUX_VAL(CP(CAM_D0),             (IEN  | PTD | DIS | M0)) /*CAM_D0*/\
 185         MUX_VAL(CP(CAM_D1),             (IEN  | PTD | DIS | M0)) /*CAM_D1*/\
 186         MUX_VAL(CP(CAM_D2),             (IEN  | PTD | DIS | M0)) /*CAM_D2*/\
 187         MUX_VAL(CP(CAM_D3),             (IEN  | PTD | DIS | M0)) /*CAM_D3*/\
 188         MUX_VAL(CP(CAM_D4),             (IEN  | PTD | DIS | M0)) /*CAM_D4*/\
 189         MUX_VAL(CP(CAM_D5),             (IEN  | PTD | DIS | M0)) /*CAM_D5*/\
 190         MUX_VAL(CP(CAM_D6),             (IEN  | PTD | DIS | M0)) /*CAM_D6*/\
 191         MUX_VAL(CP(CAM_D7),             (IEN  | PTD | DIS | M0)) /*CAM_D7*/\
 192         MUX_VAL(CP(CAM_D8),             (IEN  | PTD | DIS | M0)) /*CAM_D8*/\
 193         MUX_VAL(CP(CAM_D9),             (IEN  | PTD | DIS | M0)) /*CAM_D9*/\
 194         MUX_VAL(CP(CAM_D10),            (IEN  | PTD | DIS | M0)) /*CAM_D10*/\
 195         MUX_VAL(CP(CAM_D11),            (IEN  | PTD | DIS | M0)) /*CAM_D11*/\
 196         MUX_VAL(CP(CAM_XCLKB),          (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
 197         MUX_VAL(CP(CAM_WEN),            (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
 198         MUX_VAL(CP(CAM_STROBE),         (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
 199         MUX_VAL(CP(CSI2_DX0),           (IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
 200         MUX_VAL(CP(CSI2_DY0),           (IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
 201         MUX_VAL(CP(CSI2_DX1),           (IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
 202         MUX_VAL(CP(CSI2_DY1),           (IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
 203  /*Audio Interface */\
 204         MUX_VAL(CP(MCBSP2_FSX),         (IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
 205         MUX_VAL(CP(MCBSP2_CLKX),        (IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
 206         MUX_VAL(CP(MCBSP2_DR),          (IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
 207         MUX_VAL(CP(MCBSP2_DX),          (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
 208  /*Expansion card  */\
 209         MUX_VAL(CP(MMC1_CLK),           (IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
 210         MUX_VAL(CP(MMC1_CMD),           (IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
 211         MUX_VAL(CP(MMC1_DAT0),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
 212         MUX_VAL(CP(MMC1_DAT1),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
 213         MUX_VAL(CP(MMC1_DAT2),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
 214         MUX_VAL(CP(MMC1_DAT3),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
 215         MUX_VAL(CP(MMC1_DAT4),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
 216         MUX_VAL(CP(MMC1_DAT5),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
 217         MUX_VAL(CP(MMC1_DAT6),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
 218         MUX_VAL(CP(MMC1_DAT7),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
 219  /*Wireless LAN */\
 220         MUX_VAL(CP(MMC2_CLK),           (IEN  | PTD | DIS | M0)) /*MMC2_CLK*/\
 221         MUX_VAL(CP(MMC2_CMD),           (IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
 222         MUX_VAL(CP(MMC2_DAT0),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
 223         MUX_VAL(CP(MMC2_DAT1),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
 224         MUX_VAL(CP(MMC2_DAT2),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
 225         MUX_VAL(CP(MMC2_DAT3),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
 226         MUX_VAL(CP(MMC2_DAT4),          (IDIS | PTD | DIS | M0)) /*MMC2_DAT4*/\
 227         MUX_VAL(CP(MMC2_DAT5),          (IDIS | PTD | DIS | M0)) /*MMC2_DAT5*/\
 228         MUX_VAL(CP(MMC2_DAT6),          (IDIS | PTD | DIS | M0)) /*MMC2_DAT6 */\
 229         MUX_VAL(CP(MMC2_DAT7),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT7*/\
 230  /*Bluetooth*/\
 231         MUX_VAL(CP(MCBSP3_DX),          (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
 232         MUX_VAL(CP(MCBSP3_DR),          (IEN  | PTD | DIS | M0)) /*McBSP3_DR*/\
 233         MUX_VAL(CP(MCBSP3_CLKX),        (IEN  | PTD | DIS | M0)) /*McBSP3_CLKX  */\
 234         MUX_VAL(CP(MCBSP3_FSX),         (IEN  | PTD | DIS | M0)) /*McBSP3_FSX*/\
 235         MUX_VAL(CP(UART2_CTS),          (IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
 236         MUX_VAL(CP(UART2_RTS),          (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
 237         MUX_VAL(CP(UART2_TX),           (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
 238         MUX_VAL(CP(UART2_RX),           (IEN  | PTD | DIS | M0)) /*UART2_RX*/\
 239  /*Modem Interface */\
 240         MUX_VAL(CP(UART1_TX),           (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
 241         MUX_VAL(CP(UART1_RTS),          (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
 242         MUX_VAL(CP(UART1_CTS),          (IEN  | PTU | DIS | M0)) /*UART1_CTS*/\
 243         MUX_VAL(CP(UART1_RX),           (IEN  | PTD | DIS | M0)) /*UART1_RX*/\
 244         MUX_VAL(CP(MCBSP4_CLKX),        (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
 245                                                                  /* - LCD_INI*/\
 246         MUX_VAL(CP(MCBSP4_DR),          (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
 247                                                                  /* - LCD_ENVDD */\
 248         MUX_VAL(CP(MCBSP4_DX),          (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
 249                                                                  /* - LCD_QVGA/nVGA */\
 250         MUX_VAL(CP(MCBSP4_FSX),         (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
 251                                                                  /* - LCD_RESB */\
 252         MUX_VAL(CP(MCBSP1_CLKR),        (IEN  | PTD | DIS | M0)) /*MCBSP1_CLKR  */\
 253         MUX_VAL(CP(MCBSP1_FSR),         (IDIS | PTU | EN  | M0)) /*MCBSP1_FSR*/\
 254         MUX_VAL(CP(MCBSP1_DX),          (IDIS | PTD | DIS | M0)) /*MCBSP1_DX*/\
 255         MUX_VAL(CP(MCBSP1_DR),          (IEN  | PTD | DIS | M0)) /*MCBSP1_DR*/\
 256         MUX_VAL(CP(MCBSP_CLKS),         (IEN  | PTU | DIS | M0)) /*MCBSP_CLKS  */\
 257         MUX_VAL(CP(MCBSP1_FSX),         (IEN  | PTD | DIS | M0)) /*MCBSP1_FSX*/\
 258         MUX_VAL(CP(MCBSP1_CLKX),        (IEN  | PTD | DIS | M0)) /*MCBSP1_CLKX  */\
 259  /*Serial Interface*/\
 260         MUX_VAL(CP(UART3_CTS_RCTX),     (IEN  | PTD | EN  | M0)) /*UART3_CTS_*/\
 261                                                                  /* RCTX*/\
 262         MUX_VAL(CP(UART3_RTS_SD),       (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
 263         MUX_VAL(CP(UART3_RX_IRRX),      (IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
 264         MUX_VAL(CP(UART3_TX_IRTX),      (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
 265         MUX_VAL(CP(HSUSB0_CLK),         (IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
 266         MUX_VAL(CP(HSUSB0_STP),         (IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
 267         MUX_VAL(CP(HSUSB0_DIR),         (IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
 268         MUX_VAL(CP(HSUSB0_NXT),         (IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
 269         MUX_VAL(CP(HSUSB0_DATA0),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
 270         MUX_VAL(CP(HSUSB0_DATA1),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
 271         MUX_VAL(CP(HSUSB0_DATA2),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
 272         MUX_VAL(CP(HSUSB0_DATA3),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
 273         MUX_VAL(CP(HSUSB0_DATA4),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
 274         MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
 275         MUX_VAL(CP(HSUSB0_DATA6),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
 276         MUX_VAL(CP(HSUSB0_DATA7),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
 277         MUX_VAL(CP(I2C1_SCL),           (IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
 278         MUX_VAL(CP(I2C1_SDA),           (IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
 279         MUX_VAL(CP(I2C2_SCL),           (IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
 280         MUX_VAL(CP(I2C2_SDA),           (IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
 281         MUX_VAL(CP(I2C3_SCL),           (IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
 282         MUX_VAL(CP(I2C3_SDA),           (IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
 283         MUX_VAL(CP(I2C4_SCL),           (IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
 284         MUX_VAL(CP(I2C4_SDA),           (IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
 285         MUX_VAL(CP(HDQ_SIO),            (IEN  | PTU | EN  | M0)) /*HDQ_SIO*/\
 286         MUX_VAL(CP(MCSPI1_CLK),         (IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
 287         MUX_VAL(CP(MCSPI1_SIMO),        (IEN  | PTD | DIS | M0)) /*McSPI1_SIMO  */\
 288         MUX_VAL(CP(MCSPI1_SOMI),        (IEN  | PTD | DIS | M0)) /*McSPI1_SOMI  */\
 289         MUX_VAL(CP(MCSPI1_CS0),         (IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
 290         MUX_VAL(CP(MCSPI1_CS1),         (IEN  | PTD | EN  | M4)) /*GPIO_175*/\
 291                                                                  /* TS_PEN_IRQ */\
 292         MUX_VAL(CP(MCSPI1_CS2),         (IEN  | PTU | DIS | M4)) /*GPIO_176*/\
 293                                                                  /* - LAN_INTR*/\
 294         MUX_VAL(CP(MCSPI1_CS3),         (IEN  | PTD | EN  | M0)) /*McSPI1_CS3*/\
 295         MUX_VAL(CP(MCSPI2_CLK),         (IEN  | PTD | DIS | M0)) /*McSPI2_CLK*/\
 296         MUX_VAL(CP(MCSPI2_SIMO),        (IEN  | PTD | DIS | M0)) /*McSPI2_SIMO*/\
 297         MUX_VAL(CP(MCSPI2_SOMI),        (IEN  | PTD | DIS | M0)) /*McSPI2_SOMI*/\
 298         MUX_VAL(CP(MCSPI2_CS0),         (IEN  | PTD | EN  | M0)) /*McSPI2_CS0*/\
 299         MUX_VAL(CP(MCSPI2_CS1),         (IEN  | PTD | EN  | M0)) /*McSPI2_CS1*/\
 300  /*Control and debug */\
 301         MUX_VAL(CP(SYS_32K),            (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
 302         MUX_VAL(CP(SYS_CLKREQ),         (IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
 303         MUX_VAL(CP(SYS_NIRQ),           (IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
 304         MUX_VAL(CP(SYS_BOOT0),          (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
 305                                                                  /* - PEN_IRQ */\
 306         MUX_VAL(CP(SYS_BOOT1),          (IEN  | PTD | DIS | M4)) /*GPIO_3 */\
 307         MUX_VAL(CP(SYS_BOOT2),          (IEN  | PTD | DIS | M4)) /*GPIO_4*/\
 308         MUX_VAL(CP(SYS_BOOT3),          (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
 309         MUX_VAL(CP(SYS_BOOT4),          (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
 310         MUX_VAL(CP(SYS_BOOT5),          (IEN  | PTD | DIS | M4)) /*GPIO_7*/\
 311         MUX_VAL(CP(SYS_BOOT6),          (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
 312                                                                  /* - VIO_1V8*/\
 313         MUX_VAL(CP(SYS_OFF_MODE),       (IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
 314         MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
 315         MUX_VAL(CP(SYS_CLKOUT2),        (IEN  | PTU | EN  | M0)) /*SYS_CLKOUT2*/\
 316         MUX_VAL(CP(JTAG_nTRST),         (IEN  | PTD | DIS | M0)) /*JTAG_nTRST*/\
 317         MUX_VAL(CP(JTAG_TCK),           (IEN  | PTD | DIS | M0)) /*JTAG_TCK*/\
 318         MUX_VAL(CP(JTAG_TMS),           (IEN  | PTD | DIS | M0)) /*JTAG_TMS*/\
 319         MUX_VAL(CP(JTAG_TDI),           (IEN  | PTD | DIS | M0)) /*JTAG_TDI*/\
 320         MUX_VAL(CP(JTAG_EMU0),          (IEN  | PTD | DIS | M0)) /*JTAG_EMU0*/\
 321         MUX_VAL(CP(JTAG_EMU1),          (IEN  | PTD | DIS | M0)) /*JTAG_EMU1*/\
 322         MUX_VAL(CP(ETK_CLK_ES2),        (IDIS | PTU | EN  | M0)) /*ETK_CLK*/\
 323         MUX_VAL(CP(ETK_CTL_ES2),        (IDIS | PTD | DIS | M0)) /*ETK_CTL*/\
 324         MUX_VAL(CP(ETK_D0_ES2 ),        (IEN  | PTD | DIS | M0)) /*ETK_D0*/\
 325         MUX_VAL(CP(ETK_D1_ES2 ),        (IEN  | PTD | DIS | M0)) /*ETK_D1*/\
 326         MUX_VAL(CP(ETK_D2_ES2 ),        (IEN  | PTD | EN  | M0)) /*ETK_D2*/\
 327         MUX_VAL(CP(ETK_D3_ES2 ),        (IEN  | PTD | DIS | M0)) /*ETK_D3*/\
 328         MUX_VAL(CP(ETK_D4_ES2 ),        (IEN  | PTD | DIS | M0)) /*ETK_D4*/\
 329         MUX_VAL(CP(ETK_D5_ES2 ),        (IEN  | PTD | DIS | M0)) /*ETK_D5*/\
 330         MUX_VAL(CP(ETK_D6_ES2 ),        (IEN  | PTD | DIS | M0)) /*ETK_D6*/\
 331         MUX_VAL(CP(ETK_D7_ES2 ),        (IEN  | PTD | DIS | M0)) /*ETK_D7*/\
 332         MUX_VAL(CP(ETK_D8_ES2 ),        (IEN  | PTD | DIS | M0)) /*ETK_D8*/\
 333         MUX_VAL(CP(ETK_D9_ES2 ),        (IEN  | PTD | DIS | M0)) /*ETK_D9*/\
 334         MUX_VAL(CP(ETK_D10_ES2),        (IEN  | PTD | DIS | M0)) /*ETK_D10*/\
 335         MUX_VAL(CP(ETK_D11_ES2),        (IEN  | PTD | DIS | M0)) /*ETK_D11*/\
 336         MUX_VAL(CP(ETK_D12_ES2),        (IEN  | PTD | DIS | M0)) /*ETK_D12*/\
 337         MUX_VAL(CP(ETK_D13_ES2),        (IEN  | PTD | DIS | M0)) /*ETK_D13*/\
 338         MUX_VAL(CP(ETK_D14_ES2),        (IEN  | PTD | DIS | M0)) /*ETK_D14*/\
 339         MUX_VAL(CP(ETK_D15_ES2),        (IEN  | PTD | DIS | M0)) /*ETK_D15*/\
 340  /*Die to Die */\
 341         MUX_VAL(CP(D2D_MCAD1),          (IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
 342         MUX_VAL(CP(D2D_MCAD2),          (IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
 343         MUX_VAL(CP(D2D_MCAD3),          (IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
 344         MUX_VAL(CP(D2D_MCAD4),          (IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
 345         MUX_VAL(CP(D2D_MCAD5),          (IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
 346         MUX_VAL(CP(D2D_MCAD6),          (IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
 347         MUX_VAL(CP(D2D_MCAD7),          (IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
 348         MUX_VAL(CP(D2D_MCAD8),          (IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
 349         MUX_VAL(CP(D2D_MCAD9),          (IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
 350         MUX_VAL(CP(D2D_MCAD10),         (IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
 351         MUX_VAL(CP(D2D_MCAD11),         (IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
 352         MUX_VAL(CP(D2D_MCAD12),         (IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
 353         MUX_VAL(CP(D2D_MCAD13),         (IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
 354         MUX_VAL(CP(D2D_MCAD14),         (IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
 355         MUX_VAL(CP(D2D_MCAD15),         (IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
 356         MUX_VAL(CP(D2D_MCAD16),         (IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
 357         MUX_VAL(CP(D2D_MCAD17),         (IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
 358         MUX_VAL(CP(D2D_MCAD18),         (IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
 359         MUX_VAL(CP(D2D_MCAD19),         (IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
 360         MUX_VAL(CP(D2D_MCAD20),         (IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
 361         MUX_VAL(CP(D2D_MCAD21),         (IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
 362         MUX_VAL(CP(D2D_MCAD22),         (IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
 363         MUX_VAL(CP(D2D_MCAD23),         (IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
 364         MUX_VAL(CP(D2D_MCAD24),         (IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
 365         MUX_VAL(CP(D2D_MCAD25),         (IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
 366         MUX_VAL(CP(D2D_MCAD26),         (IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
 367         MUX_VAL(CP(D2D_MCAD27),         (IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
 368         MUX_VAL(CP(D2D_MCAD28),         (IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
 369         MUX_VAL(CP(D2D_MCAD29),         (IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
 370         MUX_VAL(CP(D2D_MCAD30),         (IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
 371         MUX_VAL(CP(D2D_MCAD31),         (IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
 372         MUX_VAL(CP(D2D_MCAD32),         (IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
 373         MUX_VAL(CP(D2D_MCAD33),         (IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
 374         MUX_VAL(CP(D2D_MCAD34),         (IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
 375         MUX_VAL(CP(D2D_MCAD35),         (IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
 376         MUX_VAL(CP(D2D_MCAD36),         (IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
 377         MUX_VAL(CP(D2D_CLK26MI),        (IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
 378         MUX_VAL(CP(D2D_NRESPWRON),      (IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
 379         MUX_VAL(CP(D2D_NRESWARM),       (IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
 380         MUX_VAL(CP(D2D_ARM9NIRQ),       (IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
 381         MUX_VAL(CP(D2D_UMA2P6FIQ),      (IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
 382         MUX_VAL(CP(D2D_SPINT),          (IEN  | PTD | EN  | M0)) /*d2d_spint*/\
 383         MUX_VAL(CP(D2D_FRINT),          (IEN  | PTD | EN  | M0)) /*d2d_frint*/\
 384         MUX_VAL(CP(D2D_DMAREQ0),        (IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
 385         MUX_VAL(CP(D2D_DMAREQ1),        (IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
 386         MUX_VAL(CP(D2D_DMAREQ2),        (IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
 387         MUX_VAL(CP(D2D_DMAREQ3),        (IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
 388         MUX_VAL(CP(D2D_N3GTRST),        (IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
 389         MUX_VAL(CP(D2D_N3GTDI),         (IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
 390         MUX_VAL(CP(D2D_N3GTDO),         (IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
 391         MUX_VAL(CP(D2D_N3GTMS),         (IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
 392         MUX_VAL(CP(D2D_N3GTCK),         (IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
 393         MUX_VAL(CP(D2D_N3GRTCK),        (IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
 394         MUX_VAL(CP(D2D_MSTDBY),         (IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
 395         MUX_VAL(CP(D2D_SWAKEUP),        (IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
 396         MUX_VAL(CP(D2D_IDLEREQ),        (IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
 397         MUX_VAL(CP(D2D_IDLEACK),        (IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
 398         MUX_VAL(CP(D2D_MWRITE),         (IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
 399         MUX_VAL(CP(D2D_SWRITE),         (IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
 400         MUX_VAL(CP(D2D_MREAD),          (IEN  | PTD | DIS | M0)) /*d2d_mread*/\
 401         MUX_VAL(CP(D2D_SREAD),          (IEN  | PTD | DIS | M0)) /*d2d_sread*/\
 402         MUX_VAL(CP(D2D_MBUSFLAG),       (IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
 403         MUX_VAL(CP(D2D_SBUSFLAG),       (IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
 404         MUX_VAL(CP(SDRC_CKE0),          (IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
 405         MUX_VAL(CP(SDRC_CKE1),          (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\
 406
 407 #endif