board/ti/omap1510inn/omap1510innovator.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
   8  *
   9  * (C) Copyright 2003
  10  * Texas Instruments, <www.ti.com>
  11  * Kshitij Gupta <Kshitij@ti.com>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <netdev.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 static void flash__init (void);
  22 static void ether__init (void);
  23
  24 static inline void delay (unsigned long loops)
  25 {
  26         __asm__ volatile ("1:\n"
  27                           "subs %0, %1, #1\n"
  28                           "bne 1b":"=r" (loops):"0" (loops));
  29 }
  30
  31 /*
  32  * Miscellaneous platform dependent initialisations
  33  */
  34
  35 int board_init (void)
  36 {
  37         /* arch number of OMAP 1510-Board */
  38         gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
  39
  40         /* adress of boot parameters */
  41         gd->bd->bi_boot_params = 0x10000100;
  42
  43 /* kk - this speeds up your boot a quite a bit.  However to make it
  44  *  work, you need make sure your kernel startup flush bug is fixed.
  45  *  ... rkw ...
  46  */
  47         icache_enable ();
  48
  49         flash__init ();
  50         ether__init ();
  51         return 0;
  52 }
  53
  54
  55 int misc_init_r (void)
  56 {
  57         /* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
  58         /* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
  59
  60         /* setup gpio direction to match board (no floats!) */
  61         /**gdir = 0xCFF9; */
  62         /**mdir = 0x103F; */
  63
  64         return (0);
  65 }
  66
  67 /******************************
  68  Routine:
  69  Description:
  70 ******************************/
  71 static void flash__init (void)
  72 {
  73 #define CS0_CHIP_SELECT_REG 0xfffecc10
  74 #define CS3_CHIP_SELECT_REG 0xfffecc1c
  75 #define EMIFS_GlB_Config_REG 0xfffecc0c
  76
  77         {
  78                 unsigned int regval;
  79
  80                 regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
  81                 regval = regval | 0x0001;       /* Turn off write protection for flash devices. */
  82                 if (regval & 0x0002) {
  83                         regval = regval & 0xfffd;       /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
  84                         /* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
  85                         /* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
  86                         /* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
  87                 }
  88                 *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
  89         }
  90 }
  91
  92
  93 /******************************
  94  Routine:
  95  Description:
  96 ******************************/
  97 static void ether__init (void)
  98 {
  99 #define ETH_CONTROL_REG 0x0800000b
 100         /* take the Ethernet controller out of reset and wait
 101          * for the EEPROM load to complete.
 102          */
 103         *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
 104         udelay (3);
 105 }
 106
 107
 108 int dram_init (void)
 109 {
 110         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 111         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 112
 113         return 0;
 114 }
 115
 116 #ifdef CONFIG_CMD_NET
 117 int board_eth_init(bd_t *bis)
 118 {
 119         int rc = 0;
 120 #ifdef CONFIG_LAN91C96
 121         rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
 122 #endif
 123         return rc;
 124 }
 125 #endif