3 * Texas Instruments Incorporated, <www.ti.com>
5 * Sricharan R <r.sricharan@ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _EVM5430_MUX_DATA_H
10 #define _EVM5430_MUX_DATA_H
12 #include <asm/arch/mux_omap5.h>
14 const struct pad_conf_entry core_padconf_array_essential
[] = {
16 {EMMC_CLK
, (PTU
| IEN
| M0
)}, /* EMMC_CLK */
17 {EMMC_CMD
, (PTU
| IEN
| M0
)}, /* EMMC_CMD */
18 {EMMC_DATA0
, (PTU
| IEN
| M0
)}, /* EMMC_DATA0 */
19 {EMMC_DATA1
, (PTU
| IEN
| M0
)}, /* EMMC_DATA1 */
20 {EMMC_DATA2
, (PTU
| IEN
| M0
)}, /* EMMC_DATA2 */
21 {EMMC_DATA3
, (PTU
| IEN
| M0
)}, /* EMMC_DATA3 */
22 {EMMC_DATA4
, (PTU
| IEN
| M0
)}, /* EMMC_DATA4 */
23 {EMMC_DATA5
, (PTU
| IEN
| M0
)}, /* EMMC_DATA5 */
24 {EMMC_DATA6
, (PTU
| IEN
| M0
)}, /* EMMC_DATA6 */
25 {EMMC_DATA7
, (PTU
| IEN
| M0
)}, /* EMMC_DATA7 */
26 {SDCARD_CLK
, (PTU
| IEN
| M0
)}, /* SDCARD_CLK */
27 {SDCARD_CMD
, (PTU
| IEN
| M0
)}, /* SDCARD_CMD */
28 {SDCARD_DATA0
, (PTU
| IEN
| M0
)}, /* SDCARD_DATA0*/
29 {SDCARD_DATA1
, (PTU
| IEN
| M0
)}, /* SDCARD_DATA1*/
30 {SDCARD_DATA2
, (PTU
| IEN
| M0
)}, /* SDCARD_DATA2*/
31 {SDCARD_DATA3
, (PTU
| IEN
| M0
)}, /* SDCARD_DATA3*/
32 {UART3_RX_IRRX
, (PTU
| IEN
| M0
)}, /* UART3_RX_IRRX */
33 {UART3_TX_IRTX
, (M0
)}, /* UART3_TX_IRTX */
34 {USBB1_HSIC_STROBE
, (PTU
| IEN
| M0
)}, /* USBB1_HSIC_STROBE */
35 {USBB1_HSIC_DATA
, (PTU
| IEN
| M0
)}, /* USBB1_HSIC_DATA */
36 {USBB2_HSIC_STROBE
, (PTU
| IEN
| M0
)}, /* USBB2_HSIC_STROBE */
37 {USBB2_HSIC_DATA
, (PTU
| IEN
| M0
)}, /* USBB2_HSIC_DATA */
38 {USBB3_HSIC_STROBE
, (PTU
| IEN
| M0
)}, /* USBB3_HSIC_STROBE*/
39 {USBB3_HSIC_DATA
, (PTU
| IEN
| M0
)}, /* USBB3_HSIC_DATA */
40 {USBD0_HS_DP
, (IEN
| M0
)}, /* USBD0_HS_DP */
41 {USBD0_HS_DM
, (IEN
| M0
)}, /* USBD0_HS_DM */
42 {USBD0_SS_RX
, (IEN
| M0
)}, /* USBD0_SS_RX */
46 const struct pad_conf_entry wkup_padconf_array_essential
[] = {
48 {SR_PMIC_SCL
, (PTU
| IEN
| M0
)}, /* SR_PMIC_SCL */
49 {SR_PMIC_SDA
, (PTU
| IEN
| M0
)}, /* SR_PMIC_SDA */
50 {SYS_32K
, (IEN
| M0
)}, /* SYS_32K */
54 const struct pad_conf_entry core_padconf_array_non_essential
[] = {
56 {C2C_DATAIN0
, (IEN
| M0
)}, /* C2C_DATAIN0 */
57 {C2C_DATAIN1
, (IEN
| M0
)}, /* C2C_DATAIN1 */
58 {C2C_DATAIN2
, (IEN
| M0
)}, /* C2C_DATAIN2 */
59 {C2C_DATAIN3
, (IEN
| M0
)}, /* C2C_DATAIN3 */
60 {C2C_DATAIN4
, (IEN
| M0
)}, /* C2C_DATAIN4 */
61 {C2C_DATAIN5
, (IEN
| M0
)}, /* C2C_DATAIN5 */
62 {C2C_DATAIN6
, (IEN
| M0
)}, /* C2C_DATAIN6 */
63 {C2C_DATAIN7
, (IEN
| M0
)}, /* C2C_DATAIN7 */
64 {C2C_CLKIN1
, (IEN
| M0
)}, /* C2C_CLKIN1 */
65 {C2C_CLKIN0
, (IEN
| M0
)}, /* C2C_CLKIN0 */
66 {C2C_CLKOUT0
, (M0
)}, /* C2C_CLKOUT0 */
67 {C2C_CLKOUT1
, (M0
)}, /* C2C_CLKOUT1 */
68 {C2C_DATAOUT0
, (M0
)}, /* C2C_DATAOUT0 */
69 {C2C_DATAOUT1
, (M0
)}, /* C2C_DATAOUT1 */
70 {C2C_DATAOUT2
, (M0
)}, /* C2C_DATAOUT2 */
71 {C2C_DATAOUT3
, (M0
)}, /* C2C_DATAOUT3 */
72 {C2C_DATAOUT4
, (M0
)}, /* C2C_DATAOUT4 */
73 {C2C_DATAOUT5
, (M0
)}, /* C2C_DATAOUT5 */
74 {C2C_DATAOUT6
, (M0
)}, /* C2C_DATAOUT6 */
75 {C2C_DATAOUT7
, (M0
)}, /* C2C_DATAOUT7 */
76 {C2C_DATA8
, (IEN
| M0
)}, /* C2C_DATA8 */
77 {C2C_DATA9
, (IEN
| M0
)}, /* C2C_DATA9 */
78 {C2C_DATA10
, (IEN
| M0
)}, /* C2C_DATA10 */
79 {C2C_DATA11
, (IEN
| M0
)}, /* C2C_DATA11 */
80 {C2C_DATA12
, (IEN
| M0
)}, /* C2C_DATA12 */
81 {C2C_DATA13
, (IEN
| M0
)}, /* C2C_DATA13 */
82 {C2C_DATA14
, (IEN
| M0
)}, /* C2C_DATA14 */
83 {C2C_DATA15
, (IEN
| M0
)}, /* C2C_DATA15 */
84 {LLIB_WAKEREQOUT
, (PTU
| IEN
| M6
)}, /* GPIO2_32 */
85 {LLIA_WAKEREQOUT
, (M1
)}, /* C2C_WAKEREQOUT */
86 {HSI1_ACREADY
, (PTD
| M6
)}, /* GPIO3_64 */
87 {HSI1_CAREADY
, (PTD
| M6
)}, /* GPIO3_65 */
88 {HSI1_ACWAKE
, (PTD
| IEN
| M6
)}, /* GPIO3_66 */
89 {HSI1_CAWAKE
, (PTU
| IEN
| M6
)}, /* GPIO3_67 */
90 {HSI1_ACFLAG
, (PTD
| IEN
| M6
)}, /* GPIO3_68 */
91 {HSI1_ACDATA
, (PTD
| M6
)}, /* GPIO3_69 */
92 {HSI1_CAFLAG
, (M6
)}, /* GPIO3_70 */
93 {HSI1_CADATA
, (M6
)}, /* GPIO3_71 */
94 {UART1_TX
, (M0
)}, /* UART1_TX */
95 {UART1_CTS
, (PTU
| IEN
| M0
)}, /* UART1_CTS */
96 {UART1_RX
, (PTU
| IEN
| M0
)}, /* UART1_RX */
97 {UART1_RTS
, (M0
)}, /* UART1_RTS */
98 {HSI2_CAREADY
, (IEN
| M0
)}, /* HSI2_CAREADY */
99 {HSI2_ACREADY
, (OFF_EN
| M0
)}, /* HSI2_ACREADY */
100 {HSI2_CAWAKE
, (IEN
| PTD
| M0
)}, /* HSI2_CAWAKE */
101 {HSI2_ACWAKE
, (M0
)}, /* HSI2_ACWAKE */
102 {HSI2_CAFLAG
, (IEN
| PTD
| M0
)}, /* HSI2_CAFLAG */
103 {HSI2_CADATA
, (IEN
| PTD
| M0
)}, /* HSI2_CADATA */
104 {HSI2_ACFLAG
, (M0
)}, /* HSI2_ACFLAG */
105 {HSI2_ACDATA
, (M0
)}, /* HSI2_ACDATA */
106 {UART2_RTS
, (IEN
| M1
)}, /* MCSPI3_SOMI */
107 {UART2_CTS
, (IEN
| M1
)}, /* MCSPI3_CS0 */
108 {UART2_RX
, (IEN
| M1
)}, /* MCSPI3_SIMO */
109 {UART2_TX
, (IEN
| M1
)}, /* MCSPI3_CLK */
110 {TIMER10_PWM_EVT
, (IEN
| M0
)}, /* TIMER10_PWM_EVT */
111 {DSIPORTA_TE0
, (IEN
| M0
)}, /* DSIPORTA_TE0 */
112 {DSIPORTA_LANE0X
, (IEN
| M0
)}, /* DSIPORTA_LANE0X */
113 {DSIPORTA_LANE0Y
, (IEN
| M0
)}, /* DSIPORTA_LANE0Y */
114 {DSIPORTA_LANE1X
, (IEN
| M0
)}, /* DSIPORTA_LANE1X */
115 {DSIPORTA_LANE1Y
, (IEN
| M0
)}, /* DSIPORTA_LANE1Y */
116 {DSIPORTA_LANE2X
, (IEN
| M0
)}, /* DSIPORTA_LANE2X */
117 {DSIPORTA_LANE2Y
, (IEN
| M0
)}, /* DSIPORTA_LANE2Y */
118 {DSIPORTA_LANE3X
, (IEN
| M0
)}, /* DSIPORTA_LANE3X */
119 {DSIPORTA_LANE3Y
, (IEN
| M0
)}, /* DSIPORTA_LANE3Y */
120 {DSIPORTA_LANE4X
, (IEN
| M0
)}, /* DSIPORTA_LANE4X */
121 {DSIPORTA_LANE4Y
, (IEN
| M0
)}, /* DSIPORTA_LANE4Y */
122 {TIMER9_PWM_EVT
, (IEN
| M0
)}, /* TIMER9_PWM_EVT */
123 {DSIPORTC_TE0
, (IEN
| M0
)}, /* DSIPORTC_TE0 */
124 {DSIPORTC_LANE0X
, (IEN
| M0
)}, /* DSIPORTC_LANE0X */
125 {DSIPORTC_LANE0Y
, (IEN
| M0
)}, /* DSIPORTC_LANE0Y */
126 {DSIPORTC_LANE1X
, (IEN
| M0
)}, /* DSIPORTC_LANE1X */
127 {DSIPORTC_LANE1Y
, (IEN
| M0
)}, /* DSIPORTC_LANE1Y */
128 {DSIPORTC_LANE2X
, (IEN
| M0
)}, /* DSIPORTC_LANE2X */
129 {DSIPORTC_LANE2Y
, (IEN
| M0
)}, /* DSIPORTC_LANE2Y */
130 {DSIPORTC_LANE3X
, (IEN
| M0
)}, /* DSIPORTC_LANE3X */
131 {DSIPORTC_LANE3Y
, (IEN
| M0
)}, /* DSIPORTC_LANE3Y */
132 {DSIPORTC_LANE4X
, (IEN
| M0
)}, /* DSIPORTC_LANE4X */
133 {DSIPORTC_LANE4Y
, (IEN
| M0
)}, /* DSIPORTC_LANE4Y */
134 {RFBI_HSYNC0
, (M4
)}, /* KBD_COL5 */
135 {RFBI_TE_VSYNC0
, (PTD
| M6
)}, /* GPIO6_161 */
136 {RFBI_RE
, (M4
)}, /* KBD_COL4 */
137 {RFBI_A0
, (PTD
| IEN
| M6
)}, /* GPIO6_165 */
138 {RFBI_DATA8
, (M4
)}, /* KBD_COL3 */
139 {RFBI_DATA9
, (PTD
| M6
)}, /* GPIO6_175 */
140 {RFBI_DATA10
, (PTD
| M6
)}, /* GPIO6_176 */
141 {RFBI_DATA11
, (PTD
| M6
)}, /* GPIO6_177 */
142 {RFBI_DATA12
, (PTD
| M6
)}, /* GPIO6_178 */
143 {RFBI_DATA13
, (PTU
| IEN
| M6
)}, /* GPIO6_179 */
144 {RFBI_DATA14
, (M4
)}, /* KBD_COL7 */
145 {RFBI_DATA15
, (M4
)}, /* KBD_COL6 */
146 {GPIO6_182
, (M6
)}, /* GPIO6_182 */
147 {GPIO6_183
, (PTD
| M6
)}, /* GPIO6_183 */
148 {GPIO6_184
, (M4
)}, /* KBD_COL2 */
149 {GPIO6_185
, (PTD
| IEN
| M6
)}, /* GPIO6_185 */
150 {GPIO6_186
, (PTD
| M6
)}, /* GPIO6_186 */
151 {GPIO6_187
, (PTU
| IEN
| M4
)}, /* KBD_ROW2 */
152 {RFBI_DATA0
, (PTD
| M6
)}, /* GPIO6_166 */
153 {RFBI_DATA1
, (PTD
| M6
)}, /* GPIO6_167 */
154 {RFBI_DATA2
, (PTD
| M6
)}, /* GPIO6_168 */
155 {RFBI_DATA3
, (PTD
| IEN
| M6
)}, /* GPIO6_169 */
156 {RFBI_DATA4
, (IEN
| M6
)}, /* GPIO6_170 */
157 {RFBI_DATA5
, (IEN
| M6
)}, /* GPIO6_171 */
158 {RFBI_DATA6
, (PTD
| M6
)}, /* GPIO6_172 */
159 {RFBI_DATA7
, (PTD
| M6
)}, /* GPIO6_173 */
160 {RFBI_CS0
, (PTD
| IEN
| M6
)}, /* GPIO6_163 */
161 {RFBI_WE
, (PTD
| M6
)}, /* GPIO6_162 */
162 {MCSPI2_CS0
, (M0
)}, /* MCSPI2_CS0 */
163 {MCSPI2_CLK
, (IEN
| M0
)}, /* MCSPI2_CLK */
164 {MCSPI2_SIMO
, (IEN
| M0
)}, /* MCSPI2_SIMO*/
165 {MCSPI2_SOMI
, (PTU
| IEN
| M0
)}, /* MCSPI2_SOMI*/
166 {I2C4_SCL
, (IEN
| M0
)}, /* I2C4_SCL */
167 {I2C4_SDA
, (IEN
| M0
)}, /* I2C4_SDA */
168 {HDMI_CEC
, (IEN
| M0
)}, /* HDMI_CEC */
169 {HDMI_HPD
, (PTD
| IEN
| M0
)}, /* HDMI_HPD */
170 {HDMI_DDC_SCL
, (IEN
| M0
)}, /* HDMI_DDC_SCL */
171 {HDMI_DDC_SDA
, (IEN
| M0
)}, /* HDMI_DDC_SDA */
172 {CSIPORTA_LANE0X
, (IEN
| M0
)}, /* CSIPORTA_LANE0X */
173 {CSIPORTA_LANE0Y
, (IEN
| M0
)}, /* CSIPORTA_LANE0Y */
174 {CSIPORTA_LANE1Y
, (IEN
| M0
)}, /* CSIPORTA_LANE1Y */
175 {CSIPORTA_LANE1X
, (IEN
| M0
)}, /* CSIPORTA_LANE1X */
176 {CSIPORTA_LANE2Y
, (IEN
| M0
)}, /* CSIPORTA_LANE2Y */
177 {CSIPORTA_LANE2X
, (IEN
| M0
)}, /* CSIPORTA_LANE2X */
178 {CSIPORTA_LANE3X
, (IEN
| M0
)}, /* CSIPORTA_LANE3X */
179 {CSIPORTA_LANE3Y
, (IEN
| M0
)}, /* CSIPORTA_LANE3Y */
180 {CSIPORTA_LANE4X
, (IEN
| M0
)}, /* CSIPORTA_LANE4X */
181 {CSIPORTA_LANE4Y
, (IEN
| M0
)}, /* CSIPORTA_LANE4Y */
182 {CSIPORTB_LANE0X
, (IEN
| M0
)}, /* CSIPORTB_LANE0X */
183 {CSIPORTB_LANE0Y
, (IEN
| M0
)}, /* CSIPORTB_LANE0Y */
184 {CSIPORTB_LANE1Y
, (IEN
| M0
)}, /* CSIPORTB_LANE1Y */
185 {CSIPORTB_LANE1X
, (IEN
| M0
)}, /* CSIPORTB_LANE1X */
186 {CSIPORTB_LANE2Y
, (IEN
| M0
)}, /* CSIPORTB_LANE2Y */
187 {CSIPORTB_LANE2X
, (IEN
| M0
)}, /* CSIPORTB_LANE2X */
188 {CSIPORTC_LANE0Y
, (IEN
| M0
)}, /* CSIPORTC_LANE0Y */
189 {CSIPORTC_LANE0X
, (IEN
| M0
)}, /* CSIPORTC_LANE0X */
190 {CSIPORTC_LANE1Y
, (IEN
| M0
)}, /* CSIPORTC_LANE1Y */
191 {CSIPORTC_LANE1X
, (IEN
| M0
)}, /* CSIPORTC_LANE1X */
192 {CAM_SHUTTER
, (M0
)}, /* CAM_SHUTTER */
193 {CAM_STROBE
, (M0
)}, /* CAM_STROBE */
194 {CAM_GLOBALRESET
, (IEN
| M0
)}, /* CAM_GLOBALRESET */
195 {TIMER11_PWM_EVT
, (PTD
| M6
)}, /* GPIO8_227 */
196 {TIMER5_PWM_EVT
, (PTD
| M6
)}, /* GPIO8_228 */
197 {TIMER6_PWM_EVT
, (PTD
| M6
)}, /* GPIO8_229 */
198 {TIMER8_PWM_EVT
, (PTU
| M6
)}, /* GPIO8_230 */
199 {I2C3_SCL
, (IEN
| M0
)}, /* I2C3_SCL */
200 {I2C3_SDA
, (IEN
| M0
)}, /* I2C3_SDA */
201 {GPIO8_233
, (IEN
| M2
)}, /* TIMER8_PWM_EVT */
202 {ABE_CLKS
, (IEN
| M0
)}, /* ABE_CLKS */
203 {ABEDMIC_DIN1
, (IEN
| M0
)}, /* ABEDMIC_DIN1 */
204 {ABEDMIC_DIN2
, (IEN
| M0
)}, /* ABEDMIC_DIN2 */
205 {ABEDMIC_DIN3
, (IEN
| M0
)}, /* ABEDMIC_DIN3 */
206 {ABEDMIC_CLK1
, (M0
)}, /* ABEDMIC_CLK1 */
207 {ABEDMIC_CLK2
, (IEN
| M1
)}, /* ABEMCBSP1_FSX */
208 {ABEDMIC_CLK3
, (M1
)}, /* ABEMCBSP1_DX */
209 {ABESLIMBUS1_CLOCK
, (IEN
| M1
)}, /* ABEMCBSP1_CLKX */
210 {ABESLIMBUS1_DATA
, (IEN
| M1
)}, /* ABEMCBSP1_DR */
211 {ABEMCBSP2_DR
, (IEN
| M0
)}, /* ABEMCBSP2_DR */
212 {ABEMCBSP2_DX
, (M0
)}, /* ABEMCBSP2_DX */
213 {ABEMCBSP2_FSX
, (IEN
| M0
)}, /* ABEMCBSP2_FSX */
214 {ABEMCBSP2_CLKX
, (IEN
| M0
)}, /* ABEMCBSP2_CLKX */
215 {ABEMCPDM_UL_DATA
, (PTD
| IEN
| OFF_EN
| OFF_PD
| OFF_IN
| M0
)}, /* ABEMCPDM_UL_DATA */
216 {ABEMCPDM_DL_DATA
, (PTD
| IEN
| OFF_EN
| OFF_PD
| OFF_IN
| M0
)}, /* ABEMCPDM_DL_DATA */
217 {ABEMCPDM_FRAME
, (PTU
| IEN
| OFF_EN
| OFF_PD
| OFF_IN
| M0
)}, /* ABEMCPDM_FRAME */
218 {ABEMCPDM_LB_CLK
, (PTD
| IEN
| OFF_EN
| OFF_PD
| OFF_IN
| M0
)}, /* ABEMCPDM_LB_CLK */
219 {WLSDIO_CLK
, (PTU
| IEN
| M0
)}, /* WLSDIO_CLK */
220 {WLSDIO_CMD
, (PTU
| IEN
| M0
)}, /* WLSDIO_CMD */
221 {WLSDIO_DATA0
, (PTU
| IEN
| M0
)}, /* WLSDIO_DATA0*/
222 {WLSDIO_DATA1
, (PTU
| IEN
| M0
)}, /* WLSDIO_DATA1*/
223 {WLSDIO_DATA2
, (PTU
| IEN
| M0
)}, /* WLSDIO_DATA2*/
224 {WLSDIO_DATA3
, (PTU
| IEN
| M0
)}, /* WLSDIO_DATA3*/
225 {UART5_RX
, (PTU
| IEN
| M0
)}, /* UART5_RX */
226 {UART5_TX
, (M0
)}, /* UART5_TX */
227 {UART5_CTS
, (PTU
| IEN
| M0
)}, /* UART5_CTS */
228 {UART5_RTS
, (M0
)}, /* UART5_RTS */
229 {I2C2_SCL
, (IEN
| M0
)}, /* I2C2_SCL */
230 {I2C2_SDA
, (IEN
| M0
)}, /* I2C2_SDA */
231 {MCSPI1_CLK
, (M6
)}, /* GPIO5_140 */
232 {MCSPI1_SOMI
, (IEN
| M6
)}, /* GPIO5_141 */
233 {MCSPI1_SIMO
, (PTD
| M6
)}, /* GPIO5_142 */
234 {MCSPI1_CS0
, (PTD
| M6
)}, /* GPIO5_143 */
235 {MCSPI1_CS1
, (PTD
| IEN
| M6
)}, /* GPIO5_144 */
236 {I2C5_SCL
, (IEN
| M0
)}, /* I2C5_SCL */
237 {I2C5_SDA
, (IEN
| M0
)}, /* I2C5_SDA */
238 {PERSLIMBUS2_CLOCK
, (PTD
| M6
)}, /* GPIO5_145 */
239 {PERSLIMBUS2_DATA
, (PTD
| IEN
| M6
)}, /* GPIO5_146 */
240 {UART6_TX
, (PTU
| IEN
| M6
)}, /* GPIO5_149 */
241 {UART6_RX
, (PTU
| IEN
| M6
)}, /* GPIO5_150 */
242 {UART6_CTS
, (PTU
| IEN
| M6
)}, /* GPIO5_151 */
243 {UART6_RTS
, (PTU
| M0
)}, /* UART6_RTS */
244 {UART3_CTS_RCTX
, (PTU
| IEN
| M6
)}, /* GPIO5_153 */
245 {UART3_RTS_IRSD
, (PTU
| IEN
| M1
)}, /* HDQ_SIO */
246 {I2C1_PMIC_SCL
, (PTU
| IEN
| M0
)}, /* I2C1_PMIC_SCL */
247 {I2C1_PMIC_SDA
, (PTU
| IEN
| M0
)}, /* I2C1_PMIC_SDA */
251 const struct pad_conf_entry wkup_padconf_array_non_essential
[] = {
254 * This pad keeps C2C Module always enabled.
255 * Putting this in safe mode do not cause the issue.
256 * C2C driver could enable this mux setting if needed.
258 {LLIA_WAKEREQIN
, (M7
)}, /* SAFE MODE */
259 {LLIB_WAKEREQIN
, (M7
)}, /* SAFE MODE */
260 {DRM_EMU0
, (PTU
| IEN
| M0
)}, /* DRM_EMU0 */
261 {DRM_EMU1
, (PTU
| IEN
| M0
)}, /* DRM_EMU1 */
262 {JTAG_NTRST
, (IEN
| M0
)}, /* JTAG_NTRST */
263 {JTAG_TCK
, (IEN
| M0
)}, /* JTAG_TCK */
264 {JTAG_RTCK
, (M0
)}, /* JTAG_RTCK */
265 {JTAG_TMSC
, (IEN
| M0
)}, /* JTAG_TMSC */
266 {JTAG_TDI
, (IEN
| M0
)}, /* JTAG_TDI */
267 {JTAG_TDO
, (M0
)}, /* JTAG_TDO */
268 {FREF_CLK_IOREQ
, (IEN
| M0
)}, /* FREF_CLK_IOREQ */
269 {FREF_CLK0_OUT
, (M0
)}, /* FREF_CLK0_OUT */
270 {FREF_CLK1_OUT
, (M0
)}, /* FREF_CLK1_OUT */
271 {FREF_CLK2_OUT
, (M0
)}, /* FREF_CLK2_OUT */
272 {FREF_CLK2_REQ
, (PTU
| IEN
| M6
)}, /* GPIO1_WK9 */
273 {FREF_CLK1_REQ
, (PTD
| IEN
| M6
)}, /* GPIO1_WK8 */
274 {SYS_NRESPWRON
, (IEN
| M0
)}, /* SYS_NRESPWRON */
275 {SYS_NRESWARM
, (PTU
| IEN
| M0
)}, /* SYS_NRESWARM */
276 {SYS_PWR_REQ
, (M0
)}, /* SYS_PWR_REQ */
277 {SYS_NIRQ1
, (PTU
| IEN
| M0
)}, /* SYS_NIRQ1 */
278 {SYS_NIRQ2
, (PTU
| IEN
| M0
)}, /* SYS_NIRQ2 */
279 {SYS_BOOT0
, (IEN
| M0
)}, /* SYS_BOOT0 */
280 {SYS_BOOT1
, (IEN
| M0
)}, /* SYS_BOOT1 */
281 {SYS_BOOT2
, (IEN
| M0
)}, /* SYS_BOOT2 */
282 {SYS_BOOT3
, (IEN
| M0
)}, /* SYS_BOOT3 */
283 {SYS_BOOT4
, (IEN
| M0
)}, /* SYS_BOOT4 */
284 {SYS_BOOT5
, (IEN
| M0
)}, /* SYS_BOOT5 */
288 #endif /* _EVM4430_MUX_DATA_H */
projects / people / ms / u-boot.git / blob